# US 11,444,063 B2 · Semiconductor package including vertical interconnector > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,063 B2 - Document ID: US11444063B2 - Status: Granted - Kind: B2 - Application number: 17/308,718 - Filed: 2021-05-05 - Published: 2022-07-21 - Granted: 2022-09-13 - Earliest claimed: 2021-01-20 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Ki Jun Sung; Chae Sung Lee - Web page: https://patentgrep.com/patent/US11444063B2 ## CPC - H10W 90/00: Package configurations - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 74/10: characterised by their shape or disposition - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/652: Cross-sectional shapes - H10W 70/6528: {of the portions that connect to chips, wafers or package parts} - H10W 70/654: Top-view layouts - H10W 70/655: Fan-out layouts - H10W 72/073: {of die-attach connectors} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/874: {On different surfaces} - H10W 72/9413: {on encapsulations} - H10W 74/114: {by a substrate and the encapsulations} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/20: Configurations of stacked chips - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package may include: at least one semiconductor chip disposed such that an active surface on which a plurality of chip pads are disposed faces a redistribution conductive layer; a plurality of vertical interconnectors, each with one end connected to a respective chip pad, extending in a vertical direction toward the redistribution conductive layer; a molding layer covering the semiconductor chip and the vertical interconnectors while exposing an other end of each of the vertical interconnectors that is not connected to the chip pad; a plurality of landing pads disposed over the molding layer, and each connected to the other end of each of the vertical interconnectors; a redistribution insulating layer covering the molding layer with an opening that collectively exposes the landing pads; and the redistribution conductive layer that extends over the molding layer and the redistribution insulating layer while being connected to each of the landing pads. ## Claims ### Claim 1 A semiconductor package comprising: at least one semiconductor chip disposed such that an active surface on which a plurality of chip pads are disposed faces a redistribution conductive layer; a plurality of vertical interconnectors, each with one end connected to a respective chip pad among the plurality of chip pads, extending in a vertical direction toward the redistribution conductive layer; a molding layer covering the semiconductor chip and the vertical interconnectors while exposing an other end of each of the vertical interconnectors that is not connected to the chip pad; a plurality of landing pads disposed over the molding layer, and each connected to the other end of each of the vertical interconnectors; a redistribution insulating layer covering the molding layer with an opening that collectively exposes the landing pads; and the redistribution conductive layer that extends over the molding layer and the redistribution insulating layer while being connected to each of the landing pads. ### Claim 2 (depends on 1) The semiconductor package according to claim 1, wherein the redistribution conductive layer is in direct contact with an upper surface and a side surface of the landing pad. ### Claim 3 (depends on 1) The semiconductor package according to claim 1, wherein the opening exposes the molding layer around the landing pads. ### Claim 4 (depends on 1) The semiconductor package according to claim 1, wherein the opening has a shape that surrounds the landing pads. ### Claim 5 (depends on 1) The semiconductor package according to claim 1, wherein a height of an upper surface of a portion of the redistribution conductive layer that is positioned in the opening is lower than a height of an upper surface of another portion of the redistribution conductive layer that is positioned outside the opening. ### Claim 6 (depends on 1) The semiconductor package according to claim 1, wherein a width of the landing pad is greater than a width of the vertical interconnector. ### Claim 7 (depends on 1) The semiconductor package according to claim 1, wherein a width of a portion of the redistribution conductive layer, which overlaps the landing pad, is smaller than a width of the landing pad. ### Claim 8 (depends on 1) The semiconductor package according to claim 1, wherein a thickness of the redistribution insulating layer is greater than a thickness of the landing pad. ### Claim 9 (depends on 1) The semiconductor package according to claim 1, wherein the at least one semiconductor chip includes first and second semiconductor chips that are stacked in an offset manner in the vertical direction to expose all of the chip pads. ### Claim 10 (depends on 9) The semiconductor package according to claim 9, wherein the redistribution conductive layer includes a first redistribution conductive layer electrically connected to the first semiconductor chip, and a second redistribution conductive layer electrically connected to the second semiconductor chip, and wherein the first redistribution conductive layer extends in an opposite direction compared to the second redistribution conductive layer. ### Claim 11 (depends on 9) The semiconductor package according to claim 9, wherein the redistribution conductive layer includes a first redistribution conductive layer electrically connected to the first semiconductor chip, and a second redistribution conductive layer electrically connected to the second semiconductor chip, wherein the first redistribution conductive layer extends in the same direction as the second redistribution conductive layer, and wherein a plurality of first redistribution conductive layers and a plurality of second redistribution conductive layers are alternately arranged to be spaced apart from each other in a direction that is perpendicular to an extension direction of the first and second redistribution conductive layers. ### Claim 12 A semiconductor package comprising: at least one semiconductor chip disposed such that an active surface on which a plurality of chip pads are disposed faces a redistribution conductive layer; a plurality of vertical interconnectors, each with one end connected to a respective chip pad among the plurality of chip pads, extending in a vertical direction toward the redistribution conductive layer; a molding layer covering the semiconductor chip and the vertical interconnectors while exposing an other end of each of the vertical interconnectors that is not connected to the chip pad; a redistribution insulating layer covering the molding layer with an opening that collectively exposes the other ends of the vertical interconnectors; and the redistribution conductive layer that extends over the molding layer and the redistribution insulating layer while being connected to each of the other ends of the vertical interconnectors. ### Claim 13 (depends on 12) The semiconductor package according to claim 12, wherein the redistribution conductive layer is in direct contact with the other end of the vertical interconnector. ### Claim 14 (depends on 12) The semiconductor package according to claim 12, wherein the opening exposes the molding layer around the vertical interconnectors. ### Claim 15 (depends on 12) The semiconductor package according to claim 12, wherein the opening has a shape that surrounds the vertical interconnectors. ### Claim 16 (depends on 12) The semiconductor package according to claim 12, wherein, in the vertical direction, a height of an upper surface of a portion of the redistribution conductive layer that is positioned in the opening, is lower than a height of an upper surface of another portion of the redistribution conductive layer that is positioned outside the opening. ### Claim 17 (depends on 12) The semiconductor package according to claim 12, wherein a width of a portion of the redistribution conductive layer, which overlaps the vertical interconnector, is greater than a width of the vertical interconnector. ### Claim 18 (depends on 12) The semiconductor package according to claim 12, wherein the redistribution conductive layer includes an end portion overlapping the vertical interconnector and a line portion that extends from the end portion, and wherein a width of the end portion is greater than a width of the line portion and a width of the vertical interconnector. ### Claim 19 (depends on 12) The semiconductor package according to claim 12, wherein the at least one semiconductor chip includes first and second semiconductor chips that are stacked in an offset manner in the vertical direction to expose all of the chip pads. ### Claim 20 (depends on 19) The semiconductor package according to claim 19, wherein the redistribution conductive layer includes a first redistribution conductive layer electrically connected to the first semiconductor chip, and a second redistribution conductive layer electrically connected to the second semiconductor chip, and wherein the first redistribution conductive layer extends in an opposite direction compared to the second redistribution conductive layer. ### Claim 21 (depends on 19) The semiconductor package according to claim 19, wherein the redistribution conductive layer includes a first redistribution conductive layer electrically connected to the first semiconductor chip, and a second redistribution conductive layer electrically connected to the second semiconductor chip, wherein the first redistribution conductive layer extends in the same direction as the second redistribution conductive layer, and wherein a plurality of first redistribution conductive layers and a plurality of second redistribution conductive layers are alternately arranged to be spaced apart from each other in a direction that is perpendicular to an extension direction of the first and second redistribution conductive layers.