# US 11,444,062 B2 · Memory scaling semiconductor device

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- Number: US 11,444,062 B2
- Document ID: US11444062B2
- Status: Granted
- Kind: B2
- Application number: 17/244,527
- Filed: 2021-04-29
- Published: 2021-08-12
- Granted: 2022-09-13
- Earliest claimed: 2019-10-07
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Nagesh Vodrahalli
- Web page: https://patentgrep.com/patent/US11444062B2

## CPC

- H10W 90/00: Package configurations
- H10B 99/22: {including field-effect components}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 72/0198: {batch processes}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/075: {of bond wires}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/551: {Materials of bond wires}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/10: characterised by their shape or disposition
- H10W 80/016: {Cleaning}
- H10W 80/031: {Changing or setting shapes of the pads}
- H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/333: {Compression bonding}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/20: Configurations of stacked chips
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. Once bonded, respective inactive surfaces of the wafers may be thinned and then the die pairs diced from the wafers to form a completed memory module. When the wafers are bonded face to face, they compensate each other, mechanically resulting in the die pair having a minimum warpage.

## Claims

### Claim 1

An integrated memory module comprising:
a first semiconductor die, comprising:
a first memory array formed in a face of the first semiconductor die, the face comprising a first surface, the first memory array having a first coefficient of thermal expansion,
a first substrate next to the first memory array and having a second coefficient of thermal expansion,
a first group of bond pads formed in the first surface of the first semiconductor die, and
electrical interconnections connected to the first group of bond pads at the first surface; and
a second semiconductor die, comprising:
a second memory array formed in a face of the second semiconductor die, the face comprising a second surface, the second memory array having a third coefficient of thermal expansion,
a second substrate next to the second memory array and having a fourth coefficient of thermal expansion, and
a second group of bond pads formed in the face of the second semiconductor die, the first and second groups of bond pads bonded to each other;
wherein the integrated memory module is configured to avoid warping by bonding the first and second semiconductor dies together face to face so that the first, second, third and fourth coefficients of thermal expansion balance each other out.

### Claim 2 (depends on 1)

The integrated memory module of claim 1, wherein the electrical connections comprise a first set of vias physically connected to the first group of bond pads at the first surface.

### Claim 3 (depends on 1)

The integrated memory module of claim 1, wherein the electrical connections comprise a first set of vias physically connected to the first group of bond pads at the first surface.

### Claim 4 (depends on 1)

The integrated memory module of claim 1, further comprising:
a third surface in the first semiconductor die opposite the first surface, and
wherein the electrical interconnections extend between the first and third surfaces.

### Claim 5 (depends on 4)

The integrated memory module of claim 4, further comprising:
a third group of bond pads formed in the third surface, the third group of bond pads configured to electrically connect the integrated memory module to a host device, and
wherein the electrical connections comprise a second set of vias physically connected to the third group of bond pads at the third surface.

### Claim 6

An integrated memory module comprising:
a first semiconductor die, comprising:
first and second opposed surfaces,
a first memory array at the first surface,
a first substrate at the second surface,
a first set of bond pads at the second surface configured to electrically connect the integrated memory module to a host device; and
a second semiconductor die, comprising:
third and fourth opposed surfaces, the first surface of the first semiconductor die bonded to the third surface of the second semiconductor die,
a second memory array at the third surface, and
a second substrate at the fourth surface;
wherein the electrical connections comprise:
a first set of electrical connections electrically coupled to the first set of bond pads and the first memory array, the first set of electrical connections configured to allow access to the first memory array independently of the second memory array,
a second set of electrical connections electrically coupled to the first set of bond pads and the second memory array, the second set of electrical connections configured to allow access to the second memory array independently of the first memory array, and
a third set of electrical connections electrically coupled to the first set of bond pads and the first and second memory arrays, the third set of electrical connections configured to allow access to the first and second memory arrays together; and
wherein the memory module is configured to be stacked in an overlapped configuration and packaged together with other memory modules that are electrically coupled to each other by the first, second, third and fourth sets of vias through the first and second semiconductor dies.

### Claim 7 (depends on 6)

The integrated memory module of claim 6, wherein the first set of electrical connections comprise a first set of vias physically connected to the first set of bond pads and the first memory array.

### Claim 8 (depends on 6)

The integrated memory module of claim 6, wherein the second set of electrical connections comprise a second set of vias physically connected to the first set of bond pads and the second memory array.

### Claim 9 (depends on 6)

The integrated memory module of claim 6, wherein the third set of electrical connections comprise a third set of vias physically connected to the first set of bond pads and the first and second memory arrays.

### Claim 10 (depends on 6)

The integrated memory module of claim 6, wherein the integrated memory module is configured to avoid warping by bonding the first and second semiconductor dies together, first surface to third surface.

### Claim 11

An integrated memory module comprising:
a first semiconductor die, comprising:
first and second opposed surfaces,
a first memory array at the first surface,
a first substrate at the second surface,
a first set of bond pads at the second surface configured to electrically connect the integrated memory module to a host device, and
electrical connections electrically coupled at least to the first set of bond pads; and
a second semiconductor die, comprising:
third and fourth opposed surfaces, the first surface of the first semiconductor die bonded to the third surface of the second semiconductor die,
a second memory array at the third surface, and
a second substrate at the fourth surface;
wherein the electrical connections comprise:
a first set of electrical connections electrically coupled to the first set of bond pads and the first memory array, the first set of electrical connections configured to allow access to the first memory array independently of the second memory array,
a second set of electrical connections electrically coupled to the first set of bond pads and the second memory array, the second set of electrical connections configured to allow access to the second memory array independently of the first memory array, and
a third set of electrical connections electrically coupled to the first set of bond pads and the first and second memory arrays, the third set of electrical connections configured to allow access to the first and second memory arrays together.

### Claim 12 (depends on 11)

The integrated memory module of claim 11, wherein the first set of electrical connections comprise a first set of vias.

### Claim 13 (depends on 11)

The integrated memory module of claim 11, wherein the second set of electrical connections comprise a second set of vias and a second set of bond pads at the first surface of the first semiconductor die, the second set of bond pads coupled to the second set of vias.

### Claim 14 (depends on 11)

The integrated memory module of claim 11, wherein the third set of electrical connections comprise a third set of vias and a third set of bond pads at the first surface of the first semiconductor die, the third set of bond pads coupled to the third set of vias.

### Claim 15 (depends on 11)

The integrated memory module of claim 11, wherein the integrated memory module is configured to avoid warping by bonding the first and second semiconductor dies together, first surface to third surface.