# US 11,444,060 B2 · Semiconductor package

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- Number: US 11,444,060 B2
- Document ID: US11444060B2
- Status: Granted
- Kind: B2
- Application number: 16/742,341
- Filed: 2020-01-14
- Published: 2021-01-14
- Granted: 2022-09-13
- Earliest claimed: 2019-07-11
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sanguk Han; Chajea Jo; Hyoeun Kim; Sunkyoung Seo
- Web page: https://patentgrep.com/patent/US11444060B2

## CPC

- H10W 90/00: Package configurations
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10P 72/7422: {used to protect an active side of a device or wafer}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/354: {comprising polymers}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/951: {Materials of bond pads}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.

## Claims

### Claim 1

A semiconductor package comprising:
a lower semiconductor package; and
an upper semiconductor package disposed on the lower semiconductor package,
wherein the lower semiconductor package includes:
a first semiconductor device including a first through electrode;
a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode;
a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device;
a second molding member contacting a sidewall of the first molding member; and
an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode, and
wherein the upper semiconductor package includes:
a third semiconductor device; and
a connection terminal electrically connected to the third semiconductor device and the upper redistribution layer.

### Claim 2 (depends on 1)

The semiconductor package according to claim 1, wherein a material of the first molding member is different from a material of the second molding member.

### Claim 3 (depends on 1)

The semiconductor package according to claim 1, wherein an upper surface of the second through electrode, an upper surface of the first molding member, and an upper surface of the second molding member are coplanar with one another.

### Claim 4 (depends on 1)

The semiconductor package according to claim 1, wherein the lower semiconductor package further includes:
a first pad disposed on the first through electrode;
a second pad disposed under the second through electrode;
a connection bump disposed between the first pad and the second pad; and
a connection layer disposed between the first semiconductor device and the second semiconductor device and covering the first pad, the second pad, and the connection bump.

### Claim 5 (depends on 1)

The semiconductor package according to claim 1, wherein a sidewall of the second semiconductor device is positioned further inward than a sidewall of the first semiconductor device,
the first molding member is disposed on the first semiconductor device and covers the second semiconductor device,
the sidewall of the first molding member is aligned with the sidewall of the first semiconductor device, and
the second molding member covers the sidewall of the first semiconductor device.

### Claim 6 (depends on 1)

The semiconductor package according to claim 1, wherein the upper semiconductor package further includes:
a third molding member covering a sidewall of the third semiconductor device; and
a heat sink disposed on the third molding member, and
wherein a sidewall of the third molding member is aligned with a sidewall of the lower semiconductor package.

### Claim 7 (depends on 1)

The semiconductor package according to claim 1, wherein the lower semiconductor package further includes:
a first protection layer disposed on the first semiconductor device and covering an upper portion of the first through electrode; and
a second protection layer disposed on the second semiconductor device and covering an upper portion of the second through electrode,
wherein an upper surface of the second protection layer is coplanar with an upper surface of the second through electrode.

### Claim 8

A semiconductor package according comprising:
a lower package; and
an upper package disposed on the lower package,
wherein the lower package includes:
a first semiconductor device including a first through electrode;
a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode;
a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device;
a second molding member covering a sidewall of the first molding member;
an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode;
a lower redistribution layer disposed below the first semiconductor device and electrically connected to the first through electrode; and
an external connection terminal electrically connected to the lower redistribution layer,
wherein the upper package includes:
a third semiconductor device; and
a first connection terminal electrically connected to the third semiconductor device and the upper redistribution layer, and
wherein an upper surface of the second through electrode is coplanar with a lower surface of the upper redistribution layer.

### Claim 9 (depends on 8)

The semiconductor package according to claim 8, wherein each of the first and second molding members is free of a through electrode.

### Claim 10 (depends on 8)

The semiconductor package according to claim 8, wherein the first molding member contacts the second molding member, and
a sidewall of the second molding member is aligned with a sidewall of the lower redistribution layer.

### Claim 11 (depends on 8)

The semiconductor package according to claim 8, wherein a sidewall of the second semiconductor device is located further inward than a sidewall of the first semiconductor device,
the first molding member is disposed on the first semiconductor device and covers the sidewall of the second semiconductor device,
the sidewall of the first molding member is aligned with the sidewall of the first semiconductor device, and
the second molding member covers the sidewall of the first semiconductor device.

### Claim 12 (depends on 8)

The semiconductor package according to claim 8, wherein the upper package further includes:
a third molding member that covers the third semiconductor device; and
a heat sink disposed on the third molding member and the third semiconductor device.

### Claim 13 (depends on 8)

The semiconductor package according to claim 8, wherein a sidewall of the upper package is located further inward than a sidewall of the second molding member.

### Claim 14

A semiconductor package comprising:
a first semiconductor device including a first through electrode;
a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode;
a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, wherein the first molding member is spaced apart from all through electrodes;
an upper redistribution layer disposed on the second semiconductor device and including an upper redistribution pattern electrically connected to the second through electrode; and
a third semiconductor device disposed on the upper redistribution layer and electrically connected to the upper redistribution pattern.

### Claim 15 (depends on 14)

The semiconductor package according to claim 14, further comprising:
a circuit substrate including an upper pad and a lower pad electrically connected to the upper pad; and
an external connection terminal electrically connected to the lower pad.

### Claim 16 (depends on 15)

The semiconductor package according to claim 15, further comprising a second molding member covering a sidewall of the first molding member and contacting the first molding member,
wherein a sidewall of the second molding member is aligned with a sidewall of the circuit substrate.

### Claim 17 (depends on 14)

The semiconductor package according to claim 14, further comprising:
a lower redistribution layer disposed below the first semiconductor device and electrically connected to the first through electrode; and
an external terminal electrically connected to the lower redistribution layer.

### Claim 18 (depends on 14)

The semiconductor package according to claim 14, further comprising:
a first pad disposed on the first through electrode;
a second pad disposed under the second through electrode;
a connection bump disposed between the first pad and the second pad; and
a connection layer disposed between the first semiconductor device and the second semiconductor device, and covering the first pad, the second pad, and the connection bump.

### Claim 19 (depends on 14)

The semiconductor package according to claim 14, wherein a sidewall of the second semiconductor device is located further inward than a sidewall of the first semiconductor device,
the first molding member is disposed on the first semiconductor device and covering the sidewall of the second semiconductor device, and
the sidewall of the first molding member is aligned with the sidewall of the first semiconductor device.

### Claim 20 (depends on 8)

The semiconductor package according to claim 8,
wherein the upper redistribution layer comprises:
a redistribution pattern that is electrically connected to the second through electrode; and
an insulation region that is on the redistribution pattern, and
wherein an upper surface of the first molding member contacts only the insulation region of the upper redistribution layer.