# US 11,444,058 B2 · Package structure with separated street between chips

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- Number: US 11,444,058 B2
- Document ID: US11444058B2
- Status: Granted
- Kind: B2
- Application number: 17/152,806
- Filed: 2021-01-20
- Published: 2022-05-12
- Granted: 2022-09-13
- Earliest claimed: 2020-11-06
- Assignees: Novatek Microelectronics Corp.
- Applicants: NOVATEK Microelectronics Corp.
- Inventors: Chien-Chen Ko; Teng-Jui Yu; Wei-Kang Tsai
- Web page: https://patentgrep.com/patent/US11444058B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/427: {Power or ground buses}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure includes a first chip and a second chip. The first chip is connected to a pair of first signal lines and a plurality of first power lines. The second chip is connected to a pair of second signal lines and a plurality of second power lines. The first chip and the second chip belong to a common wafer. A separated street is between the first chip and the second chip.

## Claims

### Claim 1

A package structure, comprising:
a first chip connected to a pair of first signal lines and a plurality of first power lines; and
a second chip connected to a pair of second signal lines and a plurality of second power lines,
wherein the first chip and the second chip belong to a common wafer, and a separated street is between the first chip and the second chip,
wherein the pair of first signal lines and the plurality of first power lines, the pair of second signal lines and the plurality of second power lines are disposed between a plurality of first pass lines and a plurality of second pass lines.

### Claim 2 (depends on 1)

The package structure of claim 1, wherein the first chip and the second chip perform the same function.

### Claim 3 (depends on 1)

The package structure of claim 1, wherein the first chip and the second chip perform different functions.

### Claim 4 (depends on 1)

The package structure of claim 1, wherein the first power lines are disposed at two sides of the pair of first signal lines.

### Claim 5 (depends on 1)

The package structure of claim 1, wherein the second power lines are disposed at two sides of the pair of second signal lines.

### Claim 6 (depends on 5)

The package structure of claim 5, wherein the separated street is between one of the first power lines and one of the second power lines.

### Claim 7 (depends on 1)

The package structure of claim 1, wherein the pair of first signal lines are adjacent to the pair of second signal lines.

### Claim 8 (depends on 7)

The package structure of claim 7, wherein the pair of first signal lines and the pair of second signal lines are disposed between the first power lines and the second power lines.

### Claim 9 (depends on 7)

The package structure of claim 7, wherein the separated street is between one of the pair of first signal lines and one of the pair of second signal lines.

### Claim 10 (depends on 1)

The package structure of claim 1, wherein separated street is an invalid circuit area.

### Claim 11 (depends on 1)

The package structure of claim 1, wherein the first chip is dependent from the second chip.

### Claim 12 (depends on 11)

The package structure of claim 11, wherein the first chip is electrically disconnected to the second chip.

### Claim 13 (depends on 1)

The package structure of claim 1, wherein a width of the separated street is less than 6 mm.

### Claim 14 (depends on 13)

The package structure of claim 13, wherein the width of the separated street is substantially in a range of 70 μm to 90 μm.

### Claim 15 (depends on 1)

The package structure of claim 1,
wherein the plurality of first pass lines are disposed at a side of the first chip, and the plurality of second pass lines are disposed at a side of the second chip, wherein the plurality of first pass lines and the plurality of second pass lines are configured to transmit signals without passing through the first chip and the second chip.

### Claim 16 (depends on 1)

The package structure of claim 1, wherein the pair of first signal lines or the pair of second signal lines are configured to receive differential signals from a timing controller of a display device, and the first power lines or the second power lines are configured to receive power signals from a power IC of the display device.

### Claim 17 (depends on 1)

The package structure of claim 1, wherein the second chip and the first chip are in a Chip-on-Film package.