# US 11,444,055 B2 · Manufacturing method of semiconductor apparatus and semiconductor apparatus

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- Number: US 11,444,055 B2
- Document ID: US11444055B2
- Status: Granted
- Kind: B2
- Application number: 17/002,189
- Filed: 2020-08-25
- Published: 2021-03-04
- Granted: 2022-09-13
- Earliest claimed: 2019-08-29
- Assignees: Canon Kabushiki Kaisha
- Applicants: Canon Kabushiki Kaisha
- Inventors: Shinichiro Watanabe; Youichi Fukaya
- Web page: https://patentgrep.com/patent/US11444055B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 72/073: {of die-attach connectors}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 72/30: Die-attach connectors
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/6523: {for connecting to pads at different heights at the same side of the package substrate, interposer or RDL}
- H10W 72/019: {of bond pads}
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/01953: {by etching}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/07331: {Connecting techniques}
- H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting}
- H10W 72/07353: {changes in shapes}
- H10W 72/321: {Structures or relative sizes of die-attach connectors}
- H10W 72/331: {Shapes of die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/354: {comprising polymers}
- H10W 72/853: {On the same surface}
- H10W 72/874: {On different surfaces}
- H10W 72/931: {Shapes of bond pads}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A manufacturing method of a semiconductor apparatus includes preparing an intermediate member that includes a first member having a first substrate comprising a semiconductor element formed thereon, a second member having a second substrate, the second substrate including a part of a circuit electrically connected to the semiconductor element and having a linear expansion coefficient different from that of the first substrate, and a third member having a third substrate showing such a linear expansion coefficient that a difference between itself and the linear expansion coefficient of the first substrate is smaller than a difference between the linear expansion coefficients of the first substrate and the second substrate, and includes bonding the first member and the second member together. A first bonding electrode containing copper electrically connected to the semiconductor element and a second bonding electrode containing copper electrically connected to the circuit are bonded together.

## Claims

### Claim 1

A manufacturing method of a semiconductor apparatus, comprising:
preparing an intermediate member that includes:
a first member including a first substrate a comprising a semiconductor element formed thereon;
a second member including a second substrate, the second substrate including a part of a circuit electrically connected to the semiconductor element and having a linear expansion coefficient different from a linear expansion coefficient of the first substrate; and
a third member including a third substrate, wherein a difference between a linear expansion coefficient of the third substrate and the linear expansion coefficient of the first substrate is smaller than a difference between the linear expansion coefficient of the first substrate and the linear expansion coefficient of the second substrate, and wherein the second member is interposed between the first member and the third member; and
heating the intermediate member to bond the first member and the second member together, so as to form a bonding including a first bonding electrode containing copper and electrically connected to the semiconductor element and a second bonding electrode containing copper and electrically connected to the circuit.

### Claim 2

A manufacturing method of a semiconductor apparatus, the method comprising:
preparing an intermediate member that includes:
a first member including a first substrate composed of a compound semiconductor and comprising a semiconductor element formed thereon;
a second member including a second substrate composed of silicon and including a part of a circuit electrically connected to the semiconductor element; and
a third member including a third substrate having a linear expansion coefficient in a range from 3×10−6/K to 6.5×10−6/K inclusive, wherein the second member is interposed between the first member and the third member; and
heating the intermediate member to bond the first member and the second member together.

### Claim 3 (depends on 1)

The manufacturing method of the semiconductor apparatus according to claim 1, wherein preparing the intermediate member includes bonding the second member and the third member at normal temperatures.

### Claim 4 (depends on 3)

The manufacturing method of the semiconductor apparatus according to claim 3, wherein bonding at normal temperatures is performed using an ultraviolet-curing adhesive.

### Claim 5 (depends on 4)

The manufacturing method of the semiconductor apparatus according to claim 4, wherein the ultraviolet-curing adhesive is light transmissive.

### Claim 6 (depends on 1)

The manufacturing method of the semiconductor apparatus according to claim 1, further comprising thinning a surface of the second substrate bonded to the third member before heating the intermediate member, the surface being on an opposite side of a surface on which the third member is mounted.

### Claim 7 (depends on 6)

The manufacturing method of the semiconductor apparatus according to claim 6, wherein a thickness of the second substrate after the thinning is smaller than a thickness of the first substrate.

### Claim 8 (depends on 6)

The manufacturing method of the semiconductor apparatus according to claim 6, further comprising forming a through electrode in the second electrode after thinning of the surface of the second substrate on the opposite side of the surface on which the third member is mounted.

### Claim 9 (depends on 1)

The manufacturing method of the semiconductor apparatus according to claim 1, wherein the semiconductor element is at least one of a light receiving element and a light emitting element.

### Claim 10 (depends on 9)

The manufacturing method of the semiconductor apparatus according to claim 9, wherein the circuit is at least one of a readout circuit configured to read out a signal of the semiconductor element and a control circuit configured to control a potential to the semiconductor element.

### Claim 11 (depends on 1)

The manufacturing method of the semiconductor apparatus according to claim 1, further comprising removing the third member after the bonding.

### Claim 12 (depends on 1)

The manufacturing method of the semiconductor apparatus according to claim 1, wherein the first substrate contains a group III-V semiconductor.

### Claim 13 (depends on 10)

The manufacturing method of the semiconductor apparatus according to claim 10,
wherein the first member includes a first insulation film on a side proximal the second member,
wherein the second member includes a second insulation film on a side proximal the second member, and
wherein in the bonding of the first member and the second member, the first insulation film and the second insulation film are bonded together.

### Claim 14

A semiconductor apparatus comprising:
a first member including a first substrate composed of a compound semiconductor and comprising a semiconductor element formed thereon;
a second member bonded to the first member and including a second substrate, the second substrate including a part of a circuit electrically connected to the semiconductor element and being composed of silicon; and
a third member bonded to the second member, and including a third substrate having a linear expansion coefficient in a range from 3×10−6/K to 6.5×10−6/K inclusive, the first member, the second member, and the third member being stacked in sequence.

### Claim 15 (depends on 14)

The semiconductor apparatus according to claim 14, wherein the third member is light transmissive.

### Claim 16 (depends on 15)

The semiconductor apparatus according to claim 15, wherein a light transmissive adhesive is arranged between the third member and the second substrate.

### Claim 17 (depends on 16)

The semiconductor apparatus according to claim 16, wherein a thickness of the second substrate is smaller than a thickness of the first substrate.

### Claim 18

A semiconductor apparatus comprising:
a first member including a first substrate composed of a compound semiconductor and comprising a semiconductor element formed thereon;
a second member bonded to the first member, the second member including a second substrate composed of silicon and comprising a part of a circuit electrically connected to the semiconductor element, wherein the first member and the second member are stacked with each other;
a first bonding electrode and a first insulation film formed on a side proximal to the second member; and
a second bonding electrode and a second insulation film formed on a side proximal to first member side,
wherein the first bonding electrode and the second bonding electrode are bonded together, and the first insulation film and the second insulation film are bonded together.

### Claim 19 (depends on 18)

The semiconductor apparatus according to claim 18, wherein the semiconductor element is at least one of a light receiving element and a light emitting element.

### Claim 20 (depends on 19)

The semiconductor apparatus according to claim 19, wherein the semiconductor element contains a group III-V semiconductor.

### Claim 21 (depends on 20)

The semiconductor apparatus according to claim 20, wherein the first bonding electrode and the second bonding electrode are composed of copper.