# US 11,444,052 B2 · Semiconductor package including a package substrate including staggered bond fingers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,052 B2 - Document ID: US11444052B2 - Status: Granted - Kind: B2 - Application number: 17/031,200 - Filed: 2020-09-24 - Published: 2021-10-21 - Granted: 2022-09-13 - Earliest claimed: 2020-04-20 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Jong Hui Kim - Web page: https://patentgrep.com/patent/US11444052B2 ## CPC - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 90/00: Package configurations - H10W 72/07141: {Means for applying energy, e.g. ovens or lasers} - H10W 72/07554: {changes in dispositions} - H10W 72/30: Die-attach connectors - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/547: {Dispositions of multiple bond wires} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a package substrate including: first and second bond finger arrays, each of the first and second finger arrays arranged in a first direction on a surface of the package substrate; a first semiconductor chip disposed on the surface of the package substrate and including a first chip pad array corresponding to the first bond finger array; a second semiconductor chip disposed on the surface of the package substrate and including a second chip pad array corresponding to the second bond finger array; first bonding wires connecting bond fingers of the first bond finger array to chip pads of the first chip pad array; and second bonding wires connecting bond fingers of the second bond finger array to chip pads of the second chip pad array. ## Claims ### Claim 1 A semiconductor package comprising: a package substrate including first and second bond finger arrays, each of the first and second bond finger arrays arranged in a first direction on a surface of the package substrate; a first semiconductor chip disposed on the surface of the package substrate and including a first chip pad array corresponding to the first bond finger array; a second semiconductor chip disposed on the surface of the package substrate and including a second chip pad array corresponding to the second bond finger array; first bonding wires connecting bond fingers of the first bond finger array to chip pads of the first chip pad array; and second bonding wires connecting bond fingers of the second bond finger array to chip pads of the second chip pad array, wherein the bond fingers of the first bond finger array and the bond fingers of the second bond finger array at least partially overlap with each other along the first direction, wherein each of the bond fingers of the first and second bond finger arrays comprises: a finger body portion having a substantially uniform width along a second direction perpendicular to the first direction; and a finger edge portion having a width that decreases along the second direction. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the bond fingers of the first bond finger array and the bond fingers of the second bond finger array at least partially overlap with each other along a second direction perpendicular to the first direction. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein each of the bond fingers of the first and second bond finger arrays has a minimum width at an end of the finger edge portion farthest from the finger body portion. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein each of the bond fingers of the first and second bond finger arrays has a hexagonal planar shape on the surface of the package substrate. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein the finger edge portions of the first bond finger array and the finger edge portions of the second bond finger array overlap with each other along the first direction. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein the finger edge portions of the first bond finger array are disposed to face the chip pads of the first chip pad array, and wherein the finger edge portions of the second bond finger array are disposed to face the chip pads of the second chip pad array. ### Claim 7 (depends on 1) The semiconductor package of claim 1, further comprising: first trace patterns extending from the bond fingers of the first bond finger array on the surface of the package substrate, the first trace patterns electrically connected to first wirings of the package substrate; and second trace patterns extending from the bond fingers of the second bond finger array on the surface of the package substrate, the second trace patterns electrically connected to second wirings of the package substrate on the surface. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the first semiconductor chip is disposed closer to the second bond finger array than the first bond finger array, and wherein the second semiconductor chip is disposed closer to the first bond finger array than the second bond finger array. ### Claim 9 (depends on 1) The semiconductor package of claim 1, wherein the bond fingers of the first bond finger array are spaced apart from the second semiconductor chip, and wherein the bond fingers of the second bond finger array are spaced apart from the first semiconductor chip. ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein first extension lines passing through central axes of the bond fingers of the first bond finger array and extending in the second direction perpendicular to the first direction are disposed to meet chip pads in the first chip pad array of the first semiconductor chip, wherein second extension lines passing through central axes of the bond fingers of the second bond finger array and extending in the second direction are disposed to meet chip pads in the second chip pad array of the second semiconductor chip, and wherein the first extension lines and the second extension lines are parallel to each other. ### Claim 11 (depends on 7) The semiconductor package of claim 7, wherein the first trace patterns extend from the finger body portions of the first bond finger array toward the second semiconductor chip, and wherein the second trace patterns extend from the finger body portions of the second bond finger array toward the first semiconductor chip. ### Claim 12 (depends on 7) The semiconductor package of claim 7, wherein the first trace patterns extend from the finger edge portions of the first bond finger array toward the first semiconductor chip, and the second trace patterns extend from the finger edge portions of the second bond finger array toward the second semiconductor chip. ### Claim 13 A semiconductor package comprising: a package substrate including first and second bond finger arrays, the first and second bond finger arrays arranged along first and second lines, respectively, in a first direction on a surface of the package substrate; a first semiconductor chip including a first chip pad array corresponding to the first bond finger array and disposed, on the surface of the package substrate, closer to the second bond finger array than the first bond finger array; a second semiconductor chip including a second chip pad array corresponding to the second bond finger array and disposed, on the surface of the package substrate, closer to the first bond finger array than the second bond finger array, and; first bonding wires connecting bond fingers of the first bond finger array to chip pads of the first chip pad array; second bonding wires connecting bond fingers of the second bond finger array to chip pads of the second chip pad array; first trace patterns extending from the bond fingers of the first bond finger array on the substrate, the first trace patterns electrically connecting the bond fingers of the first bond finger array to first wirings of the package substrate; and second trace patterns extending from the bond fingers of the second bond finger array on the substrate, the second trace patterns electrically connecting the bond fingers of the second bond finger array to second wirings of the package substrate, wherein the bond fingers of the first bond finger array and the bond fingers of the second bond finger array are staggered along the first direction, wherein each of the bond fingers of the first and second bond finger arrays comprises: a finger body portion having a substantially uniform width along a second direction perpendicular to the first direction; and a finger edge portion having a width that decreases along the second direction. ### Claim 14 (depends on 13) The semiconductor package of claim 13, wherein the finger edge portions of the first bond finger array are disposed to face the chip pads of the first chip pad array, and wherein the finger edge portions of the second bond finger array are disposed to face the chip pads of the second chip pad array. ### Claim 15 (depends on 13) The semiconductor package of claim 13, wherein the first trace patterns extend from the finger body portions of the first bond finger array toward the second semiconductor chip, and wherein the second trace patterns extend from the finger body portions of the second bond finger array toward the first semiconductor chip. ### Claim 16 (depends on 13) The semiconductor package of claim 13, wherein the bond fingers of the first bond finger array are spaced apart from the second semiconductor chip, and wherein the bond fingers of the second bond finger array are spaced apart from the first semiconductor chip. ### Claim 17 (depends on 13) The semiconductor package of claim 13, wherein first extension lines passing through central axes of the bond fingers of the first bond finger array and extending in the second direction perpendicular to the first direction are disposed to meet chip pads in the first chip pad array of the first semiconductor chip, wherein second extension lines passing through the central axes of the bond fingers of the second bond finger array and extending in the second direction are disposed to meet chip pads in the second chip pad array of the second semiconductor chip, and wherein the first extension lines and the second extension lines are parallel to each other. ### Claim 18 (depends on 14) The semiconductor package of claim 14, wherein the finger edge portions of the first and second bond finger arrays overlap with each other along the first direction.