# US 11,444,051 B2 · Fully molded semiconductor structure with face mounted passives and method of making the same

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- Number: US 11,444,051 B2
- Document ID: US11444051B2
- Status: Granted
- Kind: B2
- Application number: 17/532,475
- Filed: 2021-11-22
- Published: 2022-06-02
- Granted: 2022-09-13
- Earliest claimed: 2020-12-01
- Assignees: Deca Technologies USA, Inc.
- Applicants: Deca Technologies USA, Inc.
- Inventors: Clifford Sandstrom; Benedict San Jose; Timothy L. Olson; Craig Bishop
- Web page: https://patentgrep.com/patent/US11444051B2

## CPC

- H10W 90/00: Package configurations
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/072: {of bump connectors}
- H10W 72/07254: {changes in dispositions}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/853: {On the same surface}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/728: {between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device, and method of making the same, comprising a plurality of conductive studs formed over an active surface of a semiconductor die. The plurality of conductive studs may be disposed around a device mount site, wherein the device mount site comprises conductive interconnects comprising a height less than a height of the plurality of conductive studs. An encapsulant may be disposed around the semiconductor die and the conductive studs. A portion of the conductive studs may be exposed from the encapsulant at a planar surface. A build-up interconnect structure comprising one or more layers may be disposed over and coupled to the planar surface, the conductive studs, and the conductive interconnect. A device may be coupled to the conductive interconnects of the device mount site.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor die disposed over a first build-up interconnect structure with copper posts disposed around a perimeter of the semiconductor die;
a plurality of copper studs formed over an active surface of the semiconductor die, the plurality of copper studs being disposed around a passive mount site, wherein the passive mount site comprises copper interconnects comprising a height less than a height of the plurality of copper studs;
encapsulant disposed around the copper posts, the semiconductor die, and the copper studs, wherein a portion of the copper posts and the copper studs are exposed from the encapsulant at a planar surface;
a second build-up interconnect structure comprising one or more redistribution layers disposed over and coupled to the planar surface, the copper posts, and the copper studs;
electrical interconnects coupled to the second build-up interconnect structure; and
a passive device coupled to the copper interconnects of the passive mount site within a cavity, wherein the passive device and the copper interconnects of the passive device are exposed with respect to the encapsulant.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor die comprises a plurality of semiconductor die in a chiplet arrangement, the chiplet further comprising semiconductor die comprising one or more of: a CPU, a modem, a GPU, AI processor, TO devices, SERDES devices, and a memory device.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein:
the copper interconnects comprise a height in a range of 2 to 20 micrometers; and
the copper studs comprise a height in a range of 5 to 300 micrometers.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a footprint of the plurality of copper studs surrounds the passive mount site.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein forming the copper interconnects further comprises forming one or more bump, ball, flip chip structure, or copper pillar bump comprising one or more of solder, solderless material, polymer conductive film, and carbon.

### Claim 6 (depends on 1)

The semiconductor device of claim 1 wherein the passive device further comprises an integrated passive, resistor, capacitor, inductor, integrated passive device (IPD), multilayer ceramic capacitor (MLCC), semiconductor die, or a voltage regulator.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the passive device is directly attached to the copper interconnects of the passive mount site.

### Claim 8

A semiconductor device, comprising:
a plurality of conductive studs formed over an active surface of a semiconductor die, the plurality of conductive studs being disposed around a device mount site, wherein the device mount site comprises conductive interconnects comprising a height less than a height of the plurality of conductive studs;
encapsulant disposed around the semiconductor die and the conductive studs, wherein a portion of the conductive studs is exposed from the encapsulant at a planar surface;
a build-up interconnect structure comprising one or more layers disposed over and coupled to the planar surface, the conductive studs, and the conductive interconnects; and
a device within a cavity coupled to the conductive interconnects of the device mount site.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the semiconductor die comprises a plurality of semiconductor die in a chiplet arrangement, the chiplet further comprising semiconductor die comprising one or more of: a CPU, a modem, a GPU, AI processor, IO devices, SERDES devices, and a memory device.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein:
the conductive interconnects comprise a height in a range of 2 to 20 micrometers; and
the conductive studs comprise a height in a range of 5 to 300 micrometers.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, further comprising an underfill disposed around the device and in the device mount site to provide structural support and environmental protection for the device.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein a footprint of the plurality of conductive studs surrounds the device mount site.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein forming the conductive interconnects further comprises forming one or more bump, ball, flip chip structure, or conductive pillar bump comprising one or more of solder, solderless material, polymer conductive film, and carbon.

### Claim 14 (depends on 8)

The semiconductor device of claim 8 wherein the device further comprises an integrated passive, resistor, capacitor, inductor, integrated passive device (IPD), a multilayer ceramic capacitor (MLCC), a semiconductor die, or a voltage regulator.

### Claim 15 (depends on 8)

The semiconductor device of claim 8, wherein the device is directly attached to the conductive interconnects of the device mount site.

### Claim 16

A semiconductor device, comprising:
a plurality of conductive studs formed over an active surface of a semiconductor die, the plurality of conductive studs being disposed around a device mount site, wherein the device mount site comprises conductive interconnects comprising a height less than a height of the plurality of conductive studs;
encapsulant disposed around the semiconductor die and the conductive studs, wherein a portion of the conductive studs is exposed from the encapsulant;
a build-up interconnect structure comprising one or more conductive layers disposed over and coupled to the conductive studs;
electrical interconnects coupled to the build-up interconnect structure; and
a device coupled to the conductive interconnects of the device mount site within a cavity.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the semiconductor die comprises a plurality of semiconductor die in a chiplet arrangement, the chiplet further comprising semiconductor die comprising one or more of: a CPU, a modem, a GPU, AI processor, TO devices, SERDES devices, and a memory device.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein:
the conductive interconnects comprise a height in a range of 2 to 20 micrometers; and
the conductive studs comprise a height in a range of 5 to 300 micrometers;
wherein a footprint of the plurality of conductive studs surrounds the device mount site.

### Claim 19 (depends on 16)

The semiconductor device of claim 16 wherein the device further comprises an integrated passive, resistor, capacitor, inductor, integrated passive device (IPD), or a multilayer ceramic capacitor (MLCC), a semiconductor die or a voltage regulator.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein the device is directly attached to the conductive interconnects of the device mount site.