# US 11,444,048 B2 · Shaped interconnect bumps in semiconductor devices

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- Number: US 11,444,048 B2
- Document ID: US11444048B2
- Status: Granted
- Kind: B2
- Application number: 16/103,839
- Filed: 2018-08-14
- Published: 2019-04-11
- Granted: 2022-09-13
- Earliest claimed: 2017-10-05
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Sreenivasan K. Koduri
- Web page: https://patentgrep.com/patent/US11444048B2

## CPC

- H10W 70/042: {Etching}
- H10W 70/40: Leadframes
- H10W 70/421: {Shapes or dispositions}
- H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)}
- H10W 70/435: {of insulating layers on leadframes, e.g. bridging members}
- H10W 70/458: {of insulating layers on leadframes}
- H10W 74/016: {using moulds}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/415: {Leadframe inner leads serving as die pads}
- H10W 70/479: {on or in insulating or insulated package substrates, interposers, or redistribution layers}
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01212: {at a different location than on the final device, e.g. forming solder preforms}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/019: {of bond pads}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/07253: {changes in shapes}
- H10W 72/07255: {changes in materials}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/251: {Materials}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/267: {Multiple bump connectors having different functions}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 95/00: Packaging processes not covered by the other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In one instance, a semiconductor package includes a lead frame and a semiconductor die mounted to the lead frame via a plurality of bumps that are shaped or tapered. Each of the plurality of bumps includes a first end connected to the semiconductor die and an opposing, second end connected to the lead frame. The first end has an end surface area A1. The second end has an end surface area A2. The end surface area A1 of the first end is less than the end surface area A2 of the second end. Other aspects are disclosed.

## Claims

### Claim 1

A semiconductor package comprising:
a leadframe;
a semiconductor die mounted to the leadframe via a plurality of bumps; and
wherein each of the plurality of bumps comprises:
a first end connected to the semiconductor die, the first end having an end surface area A1, and
an opposing, second end connected to the leadframe, the second end having a end surface area A2, wherein the end surface area A1 of the first end is less than the end surface area A2 of the second end.

### Claim 2 (depends on 1)

The package of claim 1, wherein the end surface area A2 of the second end is at least 10 percent greater than the end surface area A1 of the first end.

### Claim 3 (depends on 1)

The package of claim 1, wherein the surface area A2 of the second end is at least double the surface area A1 of the first end.

### Claim 4 (depends on 1)

The package of claim 1, wherein each of the plurality of bumps is shaped as truncated cones with a large end of the truncated cone defining A2 and a narrow end of the truncated cone defining A1.

### Claim 5 (depends on 1)

The package of claim 1, wherein for each of the plurality of bumps a cross-section taken orthogonally to a line going from the first end to the second end is oval or circular.

### Claim 6 (depends on 1)

The package of claim 1, wherein the leadframe is metallic, and wherein the plurality of bumps is comprised of copper.

### Claim 7 (depends on 1)

The package of claim 1, further comprising a solder material associated with each of the plurality of bumps and wherein the solder material is disposed between the second end of the bump and the leadframe to attach the second end of the bump to the leadframe.

### Claim 8 (depends on 1)

The package of claim 1, further comprising mold compound at least partially covering the leadframe, the semiconductor die, and the plurality of bumps.

### Claim 9

A semiconductor package comprising:
a leadframe;
a semiconductor die mounted to the leadframe; and
a plurality of bumps electrically connecting the semiconductor die and the leadframe, the bumps having a longitudinal length extending from a first end to an opposing, second end, wherein the first end is connected to the semiconductor die and the second end is connected to the leadframe, and wherein the first end has a lateral width W1 orthogonal to the longitudinal length that is less than a lateral width W2 of the second end.

### Claim 10 (depends on 9)

The package of claim 9, wherein each of the plurality of bumps is tapered between the first end and the second end.

### Claim 11 (depends on 9)

The package of claim 9, wherein the first end has an end surface area A1, wherein the second end has a end surface area A2, and wherein the end surface area A1 is at least half the size of the end surface area A2.

### Claim 12 (depends on 9)

The package of claim 9, wherein for each of the plurality of bumps a cross-section taken orthogonally to a line going from the first end to the second end is oval or circular.

### Claim 13 (depends on 9)

The package of claim 9, further comprising a plurality of signal bumps electrically connecting the semiconductor die and the leadframe, the plurality of signal bumps having an average lateral width that is smaller than an average lateral width plurality of bumps.

### Claim 14 (depends on 13)

The package of claim 13, further comprising:
a solder material;
wherein the solder material is disposed between the second end of the plurality of bumps and the leadframe; and
mold compound at least partially covering the leadframe, the semiconductor die, the plurality of bumps, and the plurality of signal bumps.

### Claim 15 (depends on 9)

The package of claim 9, wherein the leadframe is metallic.