# US 11,444,045 B2 · Bonding structures of semiconductor devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,045 B2 - Document ID: US11444045B2 - Status: Granted - Kind: B2 - Application number: 16/994,644 - Filed: 2020-08-16 - Published: 2022-02-17 - Granted: 2022-09-13 - Earliest claimed: 2020-08-16 - Assignees: Globalfoundries Singapore Pte. Ltd. - Applicants: GLOBALFOUNDRIES Singapore Pte. Ltd. - Inventors: Ramasamy Chockalingam; Juan Boon Tan; Xiaodong Li; Kai Chong Chan; Ranjan Rajoo - Web page: https://patentgrep.com/patent/US11444045B2 ## CPC - H10W 72/90: Bond pads, in general - H10W 72/50: Bond wires - H10W 72/01908: {using permanent auxiliary members, e.g. using alignment marks} - H10W 72/01935: {by plating, e.g. electroless plating or electroplating} - H10W 72/01951: {Changing the shapes of bond pads} - H10W 72/01953: {by etching} - H10W 72/01955: {by using masks} - H10W 72/01961: {Chemical or physical modification, e.g. by sintering or anodisation (patterning H10W72/01951)} - H10W 72/075: {of bond wires} - H10W 72/07533: {Ultrasonic bonding, e.g. thermosonic bonding} - H10W 72/552: {comprising metals or metalloids, e.g. silver} - H10W 72/5522: {comprising gold [Au]} - H10W 72/5525: {comprising copper [Cu]} - H10W 72/555: {of outermost layers of multilayered bond wires, e.g. material of a coating} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/951: {Materials of bond pads} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/147: {the encapsulations being multilayered} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device is provided that includes a bond pad, an insulating layer, and a bonding structure. The bond pad is in a dielectric layer and the insulating layer is over the bond pad; the insulating layer having an opening over the bond pad formed therein. The bonding structure electrically couples the bond pad in the opening. The bonding structure has a height that at least extends to an upper surface of the insulating layer. ## Claims ### Claim 1 A semiconductor device comprising: a bond pad in a dielectric layer; a passivation layer over the dielectric layer and the bond pad; an insulating layer over the passivation layer; a bonding structure through the passivation layer and the insulating layer, wherein the bonding structure has a height that at least extends to an upper surface of the insulating layer and is electrically coupled with the bond pad; and a dielectric barrier liner over an upper surface of the bonding structure. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the bonding structure has a first width defined by an opening in the passivation layer and a second width defined by an opening in the insulating layer, the first width being narrower than the second width. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein the first width is less than the width of the bond pad. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the bond pad and the bonding structure comprise the same conductive material. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein the conductive material is copper. ### Claim 6 (depends on 1) The semiconductor device of claim 1, further comprises a bonding wire directly over the bond pad. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein the bonding wire comprises a same conductive material as the bonding structure. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the bonding structure abuts upon the bond pad. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein the bonding structure has an upper surface that is substantially coplanar with the upper surface of the insulating layer. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein a portion of the bonding structure overlays the insulating layer. ### Claim 11 (depends on 1) The semiconductor device of claim 1, further comprises an adhesion layer between the bonding structure and the bond pad. ### Claim 12 A method of forming a semiconductor device, comprising: forming a bond pad formed in a dielectric layer; forming a passivation layer over the dielectric layer and the bond pad; forming an insulating layer over the passivation layer; forming an opening in the passivation layer and the insulating layer to expose the bond pad; forming a bonding structure in the opening electrically coupling the bond pad, wherein the bonding structure has a height that at least extends to an upper surface of the insulating layer; and forming a dielectric barrier liner over an upper surface of the bonding structure. ### Claim 13 (depends on 12) The method of claim 12, wherein the formation of the bonding structure further comprises forming an upper surface that is substantially coplanar with the upper surface of the insulating layer. ### Claim 14 (depends on 13) The method of claim 13, wherein the formation of the substantially coplanar upper surface of the bonding structure comprises a mechanical material removing process. ### Claim 15 (depends on 14) The method of claim 14, wherein the mechanical material removing process comprises a diamond bit cutting process. ### Claim 16 (depends on 12) The method of claim 12, wherein the formation of the bonding structure comprises electroless plating of conductive material onto the bond pad. ### Claim 17 (depends on 12) The method of claim 12, further comprises forming a conformal adhesion layer in the opening and over the insulating layer. ### Claim 18 (depends on 17) The method of claim 17, further comprises electroplating a conductive material onto the adhesion layer to at least fill the opening. ### Claim 19 A semiconductor device comprising: a bond pad in a dielectric layer; a passivation layer over the dielectric layer and the bond pad; an insulating layer over the passivation layer, the insulating layer having an upper surface; an opening through the passivation layer and the insulating layer, the opening exposes the bond pad; a bonding structure having a uniform material composition in the opening, wherein the bonding structure at least fills to the top of the opening with a height that at least extends to the upper surface of the insulating layer and is electrically coupled with the bond pad; and a barrier liner over the bonding structure. ### Claim 20 (depends on 19) The semiconductor device of claim 19, wherein the barrier liner comprises a dielectric or a transition metal.