# US 11,444,041 B2 · Process of realization of an area of individualization of an integrated circuit

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- Number: US 11,444,041 B2
- Document ID: US11444041B2
- Status: Granted
- Kind: B2
- Application number: 17/216,794
- Filed: 2021-03-30
- Published: 2021-12-02
- Granted: 2022-09-13
- Earliest claimed: 2020-03-30
- Assignees: Commissariat A L'energie Atomique Et Aux Energies Alternatives
- Applicants: Commissariat A L'energie Atomique Et Aux Energies Alternatives
- Inventors: Hubert Teyssedre; Stefan Landis; Michael May
- Web page: https://patentgrep.com/patent/US11444041B2

## CPC

- G03F 7/0002: {Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping}
- H10W 42/40: protecting against tampering, e.g. unauthorised inspection or reverse engineering
- G06F 21/73: by creating or determining hardware identification, e.g. serial numbers
- H04L 9/3278: {using physically unclonable functions [PUF]}
- H10P 76/20: of masks comprising organic materials
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/091: {by printing or stamping}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- B82Y 40/00: Manufacture or treatment of nanostructures
- H04L 2209/12: Details relating to cryptographic hardware or logic circuitry
- H10W 20/43: Layouts of interconnections
- H10W 46/403: {for non-wireless electrical read out}
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method for producing an individualisation area includes providing at least a first level of the electrical tracks. The method includes depositing a dielectric layer and a deformable layer on the interconnection level. The method includes producing, in an area of the deformable layer, recessed patterns, by penetrating an imprint mould into the deformable layer, the production of the patterns being configured so that the patterns have a randomness in the deformable layer, thus forming random patterns. The method includes transferring the random patterns into the dielectric layer to form transferred random patterns therein and exposing the vias located in line with the transferred random patterns. The method includes filling the transferred random patterns with an electrically conductive material so as to form electrical connections between vias. The method includes producing a second level of the electrical tracks on the vias and the electrical connections.

## Claims

### Claim 1

A method for producing an individualisation area on an integrated circuit, the integrated circuit being intended to comprise at least:
a first and a second level of electrical tracks,
an interconnection level located between the first and second levels of the electrical tracks and including vias intended to electrically connect the electrical tracks of the first level with electrical tracks of the second level,
the method comprising at least the following steps:
providing at least the first level of the electrical tracks, then providing the interconnection level comprising the vias,
depositing at least one deformable layer and one dielectric layer on the interconnection level,
producing, in an area of the deformable layer intended to comprise the individualisation area, recessed patterns, by penetrating an imprint mould into the deformable layer, the production of the recessed patterns being configured so that the patterns have a randomness in the deformable layer, thus forming random patterns and that at least some random patterns extend in line with at least two vias of the interconnection level,
transferring the random patterns into the dielectric layer to form transferred random patterns therein and exposing the vias located in line with the transferred random patterns,
filling the transferred random patterns with an electrically conductive material so as to form electrical connections between vias,
producing the second level of the electrical tracks on the vias and the electrical connections,
and said production of the patterns so that the patterns have a randomness in the deformable layer, comprises the following steps:
providing said imprint mould, said mould having a front face carrying initial reliefs,
achieving a random collapse of the initial reliefs so as to form random reliefs,
penetrating the front face of the mould into the deformable layer to leave the random patterns therein,
the step of achieving the random collapse of the initial reliefs of the mould being carried out before and/or during the penetration of the front face of the mould into the deformable layer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the initial reliefs have a shape ratio greater than or equal to 2 and preferably greater than or equal to 5.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the step of achieving the random collapse of the initial reliefs of the mould is carried out, at least partly and preferably only, before the penetration of the mould into the deformable layer.

### Claim 4 (depends on 3)

The method according to claim 3, wherein the initial reliefs are dipped in a liquid before the penetration of the mould into the deformable layer.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the step of achieving the random collapse of the initial reliefs of the mould is carried out, at least partly and preferably only, during the penetration of the mould into the deformable layer.

### Claim 6 (depends on 5)

The method according to claim 5, wherein the random collapse of the initial reliefs is obtained by the penetration of the initial reliefs into the deformable layer.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the step of achieving the random collapse of the initial reliefs of the mould is carried out partly before the penetration of the mould into the deformable layer and partly during the penetration of the mould into the deformable layer.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the production of the random patterns is carried out only in at least one individualisation area, and the integrated circuit has at least one other area, distinct from the individualisation area, preferably intended to form a functional area for the integrated circuit, the first and the second levels of electrical tracks as well as the interconnection level extending into said at least one other area.

### Claim 9 (depends on 1)

The method according to claim 1, comprising the following steps carried out before the step of providing the imprint mould:
providing a master having reliefs,
penetrating a layer of deformable material into the reliefs of the master in order to reproduce the initial reliefs of the mould therein, the layer of deformable material forming at least part of the mould having the initial reliefs,
separating the mould and the master.

### Claim 10 (depends on 9)

The method according to claim 9, wherein the initial reliefs have parameters selected so as to promote the randomness of the collapse, the parameters being taken from: a shape ratio of the initial reliefs, a critical dimension of the initial reliefs, a material constituting the initial reliefs, a Young's modulus of the initial reliefs, and a temperature of the initial reliefs.

### Claim 11 (depends on 9)

The method according to claim 9, wherein the reliefs of the master are covered with a non-stick layer and the step of separating the mould and the master is carried out so that molecules of the non-stick layer remain on the initial reliefs of the mould after separation of the mould and the master.

### Claim 12 (depends on 9)

The method according to claim 9, wherein to achieve the random collapse of the initial reliefs, the initial reliefs of the mould are penetrated into a deformable layer or in a liquid.

### Claim 13 (depends on 1)

A method for producing a microelectronic device including at least one integrated circuit, the integrated circuit including at least:
a first and a second level of the electrical tracks,
an interconnection level located between the first and second levels of the electrical tracks and including vias intended to electrically connect the tracks of the first level with the tracks the second level,
an individualisation area produced by implementing the method according to claim 1 on only part of the integrated circuit, and
a functional area distinct from the individualisation area and comprising microelectronic structures taken from transistors, diodes, MEMS or MOEMS.