# US 11,444,040 B2 · Method for manufacturing a microelectronic device integrating a physical unclonable function provided by resistive memories, and said device

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- Number: US 11,444,040 B2
- Document ID: US11444040B2
- Status: Granted
- Kind: B2
- Application number: 17/027,193
- Filed: 2020-09-21
- Published: 2021-03-25
- Granted: 2022-09-13
- Earliest claimed: 2019-09-23
- Assignees: Commissariat A L'energie Atomique Et Aux Energies Alternatives
- Applicants: Commissariat à L'éNergie Atomique Et Aux éNergies Alternatives
- Inventors: Christelle Charpin-Nicolle; Florian Pebay-Peyroula
- Web page: https://patentgrep.com/patent/US11444040B2

## CPC

- H04L 9/3278: {using physically unclonable functions [PUF]}
- H10W 42/40: protecting against tampering, e.g. unauthorised inspection or reverse engineering
- G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00)
- H04L 9/0866: {involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8418: {adapted for focusing electric field or current, e.g. tip-shaped}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H04L 2209/12: Details relating to cryptographic hardware or logic circuitry
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A microelectronic device and method for manufacturing a microelectronic device comprising a plurality of resistive memories, a part of these resistive memories, called PUF memories, forming a PUF, the rest of these resistive memories being known as storage memories. The manufacturing process comprising forming a dielectric layer having on at least one contact surface in contact with an electrode a surface roughness of said surface greater than that of the same dielectric layer of the storage memories.

## Claims

### Claim 1

A method for manufacturing a microelectronic device comprising a plurality of resistive memories, a first part of these resistive memories being configured to form an unclonable physical function, better known as the acronym PUF, the resistive memories of said first part of resistive memories being said PUF memories, a second part of resistive memories being to provide a memory function to the microelectronic device, the resistive memories of the second part being called storage memories, the manufacturing method comprising the following steps of:
providing a support comprising a plurality of first metal electrodes,
for each first electrode, forming a dielectric layer portion comprising a first contact surface facing the corresponding first electrode and a second surface opposite to the first contact surface, the dielectric layer portions for forming the PUF memories having, on at least one of the first contact surface and the second surface, a surface roughness greater than that of the same surface of the dielectric layer portions for forming the storage memories,
for each dielectric layer portion, forming a second electrode facing the second surface, said second surface then being a second contact surface facing the second electrode and the dielectric layer portion being interposed between the first and second electrodes, the resistive memories being thus formed.

### Claim 2 (depends on 1)

The method for manufacturing a microelectronic device according to claim 1, wherein the step of forming the dielectric layer portion for each first electrode comprises the following sub-steps of:
structuring a surface of each first electrode corresponding to the PUF memories so that said first electrodes corresponding to the PUF memories have a surface roughness greater than the surface of the first electrodes corresponding to the storage memories,
depositing each dielectric layer portion in contact with the first surface of the corresponding first electrode in such a way that the roughness of the surface of the first electrode is at least partially transferred to the first contact surface of the corresponding dielectric layer portion, this transferred roughness being, for dielectric layer portions for forming the PUF memories, greater than the transferred roughness for the dielectric layer portions for forming the storage memories.

### Claim 3 (depends on 2)

The method for manufacturing a microelectronic device according to claim 2, wherein the substep of structuring the surface of each first electrode corresponding to a PUF memory is provided by etching the first electrodes for forming the PUF memories.

### Claim 4 (depends on 2)

The method for manufacturing a microelectronic device according to claim 2, wherein the surface of the first electrodes is etched by means of a plasma etching or reactive ion etching technique.

### Claim 5 (depends on 2)

The method for manufacturing a microelectronic device according to claim 2, wherein during the substep of depositing each dielectric layer portion, depositing a dielectric material forming the dielectric layer portions is carried out by atomic layer deposition.

### Claim 6 (depends on 2)

The method for manufacturing a microelectronic device according to claim 2, wherein during the substep of depositing each dielectric layer portion, depositing a dielectric material forming the dielectric layer portions is carried out by physical vapour deposition.

### Claim 7 (depends on 2)

The method for manufacturing a microelectronic device according to claim 2, wherein during the step of forming the dielectric layer portion for each first electrode:
prior to the sub-step of structuring a surface of the first electrodes, a sub-step of protecting the first electrodes for the formation of the storage memories in order to protect said first electrodes during the sub-step of structuring the surface of the first electrodes, and
between the sub-steps of structuring and depositing each dielectric layer portion, there is a sub-step of removing the protection of the first electrodes for forming the storage memories.

### Claim 8 (depends on 1)

The method for manufacturing a microelectronic device according to claim 1, wherein the resistive memories are oxide-based resistive memories,
and wherein in the step of forming the dielectric layer portion for each first electrode, for each dielectric layer portion for forming a PUF memory, the at least one surface of the first contact surface and the second surface has a mean roughness deviation Ra value of between 1 and 3 nm, 1 and 3 nm included.

### Claim 9 (depends on 1)

The manufacturing method according to claim 1, wherein the resistive memories are conductive bridging resistive memories.

### Claim 10 (depends on 1)

The method for manufacturing a microelectronic device according to claim 1, wherein there are additionally provided the following steps of:
applying a forming voltage between the first and second electrodes of each of the PUF memories, this voltage being adapted to allow the formation of substantially one half of the PUF memories,
applying a forming voltage higher than a minimum storage memory forming voltage between the first and second electrode of each of the storage memories.

### Claim 11 (depends on 1)

The method for manufacturing a microelectronic device according to claim 1, wherein the step of forming a dielectric layer portion for each first electrode comprises a substep of forming, for each of the dielectric layer portions for forming a PUF memory, an additional dielectric layer portion in such a manner that this additional dielectric layer portion is disposed between the first contact surface and the first electrode.

### Claim 12

A microelectronic device comprising a plurality of resistive memories, a first part of these resistive memories being configured to form an unclonable physical function, better known as the acronym PUF, the resistive memories of said first part of resistive memories being called PUF memories, a second part of resistive memories being to provide a memory function to the microelectronic device, the resistive memories of the second part being called storage memories, the device comprising a support, each resistive memory comprising:
a first metal electrode and a second metal electrode, the first electrode being arranged in a support,
a dielectric layer portion interposed between the first and second electrodes and having a first contact surface facing the first electrode and a second contact surface facing the second electrode,
wherein the dielectric layer portions of the PUF memories have, on at least one of the first contact surface and the second contact surface, a surface roughness of said surface greater than that of the same surface of the dielectric layer portions of the storage memories.

### Claim 13 (depends on 12)

The microelectronic device according to claim 12, wherein the resistive memories are oxide-based resistive memories,
and wherein the dielectric layer portions of the PUF memories have on at least one of the first and second contact surfaces a mean roughness deviation Ra value of between 1 and 3 nm, 2 and 3 nm included.

### Claim 14 (depends on 12)

The microelectronic device according to claim 12, wherein the resistive memories are conductive bridging resistive memories.

### Claim 15 (depends on 12)

The microelectronic device according to claim 12, wherein the PUF memories each further comprise an additional dielectric layer portion disposed between a first contact surface facing the first electrode.