# US 11,444,039 B2 · Semiconductor die including diffusion barrier layers embedding bonding pads and methods of forming the same

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- Number: US 11,444,039 B2
- Document ID: US11444039B2
- Status: Granted
- Kind: B2
- Application number: 16/888,055
- Filed: 2020-05-29
- Published: 2021-12-02
- Granted: 2022-09-13
- Earliest claimed: 2020-05-29
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Noriaki Oda; Teruo Okina
- Web page: https://patentgrep.com/patent/US11444039B2

## CPC

- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 90/00: Package configurations
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01953: {by etching}
- H10W 72/874: {On different surfaces}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9232: {with additional elements interposed between layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/732: {having shape changed during the connecting}
- H10W 90/20: Configurations of stacked chips
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices can be formed over a semiconductor substrate, and interconnect-level dielectric material layers embedding metal interconnect structures can be formed thereupon. In one embodiment, a pad-connection-via-level dielectric material layer, a proximal dielectric diffusion barrier layer, and a pad-level dielectric material layer can be formed. Bonding pads surrounded by dielectric diffusion barrier portions can be formed in the pad-level dielectric material layer. In another embodiment, a layer stack of a proximal dielectric diffusion barrier layer and a pad-and-via-level dielectric material layer can be formed. Integrated pad and via cavities can be formed through the pad-and-via-level dielectric material layer, and can be filled with bonding pads containing dielectric diffusion barrier portions and integrated pad and via structures.

## Claims

### Claim 1

A structure comprising a first semiconductor die, wherein the first semiconductor die comprises:
first semiconductor devices located over a first substrate;
first interconnect-level dielectric material layers embedding first metal interconnect structures that are electrically connected to the first semiconductor devices and overlie the first semiconductor devices;
a layer stack of a first pad-connection-via-level dielectric material layer and a first proximal dielectric diffusion barrier layer overlying the first interconnect-level dielectric material layers and embedding first pad-connection via structures; and
a first pad-level dielectric material layer including first pad cavities that are filled with a respective combination of a first bonding pad and a respective first dielectric diffusion barrier portion, wherein each of the first bonding pads contacts a respective subset of the first pad-connection via structures;
wherein each of the first dielectric diffusion barrier portions comprises sidewall segments in contact with the first pad-level dielectric material layer and extending from a bottom surface of the first pad-level dielectric material layer to a top surface of the first pad-level dielectric material layer; and
wherein each of the first dielectric diffusion barrier portions further comprises a horizontal segment having a bottom surface that contacts the first proximal dielectric diffusion barrier layer, wherein the bottom surface comprises an outer periphery that is adjoined to bottom edges of the sidewall segments and an inner periphery that is laterally offset inward from the outer periphery by an offset distance that is greater than a thickness of the sidewall segments of the first dielectric diffusion barrier portions.

### Claim 2 (depends on 1)

The structure of claim 1, further comprising a second semiconductor die comprising:
second semiconductor devices located over a second substrate;
second interconnect-level dielectric material layers embedding second metal interconnect structures that are electrically connected to the second semiconductor devices; and
second bonding pads that are electrically connected to the second metal interconnect structures and bonded to a respective one of the first bonding pads.

### Claim 3 (depends on 2)

The structure of claim 2, wherein:
the first semiconductor devices comprise either three-dimensional memory devices or driver circuit devices for the three-dimensional memory devices;
the second semiconductor devices comprise another one of the three-dimensional memory devices or the driver circuit devices for the three-dimensional memory devices;
each of the second bonding pads contacts, and is laterally surrounded by, a respective second dielectric diffusion barrier portion;
the second bonding pads and the second dielectric diffusion barrier portions are embedded in a second pad-level dielectric material layer;
the second semiconductor die comprises a layer stack of a second pad-connection-via-level dielectric material layer and a second proximal dielectric diffusion barrier layer located between the second interconnect-level dielectric material layers and the second pad-level dielectric material layer and embedding second pad-connection via structures, and
each of the second bonding pads contacts a respective subset of the second pad-connection via structures.

### Claim 4

A structure comprising a first semiconductor die, wherein the first semiconductor die comprises:
first semiconductor devices located over a first substrate;
first interconnect-level dielectric material layers embedding first metal interconnect structures that are electrically connected to the first semiconductor devices and overlie the first semiconductor devices;
a layer stack of a first pad-connection-via-level dielectric material layer and a first proximal dielectric diffusion barrier layer overlying the first interconnect-level dielectric material layers and embedding first pad-connection via structures; and
a first pad-level dielectric material layer including first pad cavities that are filled with a respective combination of a first bonding pad and a respective first dielectric diffusion barrier portion, wherein each of the first bonding pads contacts a respective subset of the first pad-connection via structures;
wherein the first semiconductor die comprises:
an additional planar diffusion barrier layer located between the first interconnect-level dielectric material layers and the first pad-connection-via-level dielectric material layer; and
at least one edge seal structure comprising a respective subset of the first metal interconnect structures that provides a respective continuous barrier laterally surrounding the first semiconductor devices without any lateral opening and vertically extends from the first substrate to the additional planar diffusion barrier layer.

### Claim 5 (depends on 4)

The structure of claim 4, wherein the at least one edge seal structure is electrically grounded.

### Claim 6 (depends on 4)

The structure of claim 4, further comprising a second semiconductor die comprising:
second semiconductor devices located over a second substrate;
second interconnect-level dielectric material layers embedding second metal interconnect structures that are electrically connected to the second semiconductor devices; and
second bonding pads that are electrically connected to the second metal interconnect structures and bonded to a respective one of the first bonding pads.

### Claim 7 (depends on 6)

The structure of claim 6, wherein:
the first semiconductor devices comprise either three-dimensional memory devices or driver circuit devices for the three-dimensional memory devices;
the second semiconductor devices comprise another one of the three-dimensional memory devices or the driver circuit devices for the three-dimensional memory devices;
each of the second bonding pads contacts, and is laterally surrounded by, a respective second dielectric diffusion barrier portion;
the second bonding pads and the second dielectric diffusion barrier portions are embedded in a second pad-level dielectric material layer;
the second semiconductor die comprises a layer stack of a second pad-connection-via-level dielectric material layer and a second proximal dielectric diffusion barrier layer located between the second interconnect-level dielectric material layers and the second pad-level dielectric material layer and embedding second pad-connection via structures, and
each of the second bonding pads contacts a respective subset of the second pad-connection via structures.