# US 11,444,038 B2 · Forming large chips through stitching

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- Number: US 11,444,038 B2
- Document ID: US11444038B2
- Status: Granted
- Kind: B2
- Application number: 16/704,303
- Filed: 2019-12-05
- Published: 2020-04-09
- Granted: 2022-09-13
- Earliest claimed: 2016-01-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Wen Hsin Wei; Hsien-Pin Hu; Shang-Yun Hou; Weiming Chris Chen
- Web page: https://patentgrep.com/patent/US11444038B2

## CPC

- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 20/085: {involving intermediate temporary filling with material}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 72/00: Interconnections or connectors in packages
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/48: Insulating materials thereof
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/66: Conductive materials thereof
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/019: {of bond pads}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/0198: {batch processes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/237: {Multiple bump connectors having different shapes}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.

## Claims

### Claim 1

A method comprising:
forming a first dielectric layer over a substrate, wherein the first dielectric layer extends into a first device region and a second device region;
forming a photo resist comprising:
a first part in the first device region; and
a second part in the second device region;
forming a first metal line in the first dielectric layer, wherein the first metal line is in the first device region, and wherein the forming the first metal line comprises a first process, and the first process comprises a first light-exposure process using a first lithograph mask to expose the first part of the photo resist;
forming a second metal line in the first dielectric layer, wherein the second metal line is in the second device region, wherein the forming the second metal line comprises a second process separate from the first process, and wherein the second process comprises a second light-exposure process using a second lithograph mask to expose the second part of the photo resist; and
forming a seal ring comprising a first portion in the first dielectric layer, wherein the first portion of the seal ring encircles both of the first metal line and the second metal line.

### Claim 2 (depends on 1)

The method of claim 1, wherein both of the first dielectric layer and the photo resist extends into a third device region between the first device region and the second device region, and wherein a third portion of the photo resist in the third device region is exposed during both of the first light-exposure process and the second light-exposure process.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first lithograph mask and the second lithograph mask have different patterns.

### Claim 4 (depends on 1)

The method of claim 1, wherein an entirety of the first dielectric layer is deposited in a same deposition process.

### Claim 5 (depends on 1)

The method of claim 1 further comprising:
when the first metal line is formed, simultaneously forming an additional first part of the first portion of the seal ring in the first dielectric layer; and
when the second metal line is formed, simultaneously forming an additional second part of the first portion of the seal ring in the first dielectric layer.

### Claim 6 (depends on 1)

The method of claim 1 further comprising forming a second dielectric layer over the substrate, wherein a second portion of the seal ring extends into the second dielectric layer.

### Claim 7 (depends on 1)

The method of claim 1 further comprising performing a die-saw process to form a package, with the seal ring formed in a peripheral region of the package.

### Claim 8 (depends on 7)

The method of claim 7, wherein the seal ring comprises four sides, and the die-saw process is performed proximal the four sides of the seal ring.

### Claim 9

A method comprising:
forming a dielectric layer over a substrate;
performing a first light-exposure process on a first portion of a photo resist;
performing a second light-exposure process on a second portion of the photo resist;
developing the photo resist to remove the first portion and the second portion of the photo resist, wherein a trench ring is formed in the photo resist;
etching the dielectric layer using the photo resist as an etching mask to extend the trench ring into the dielectric layer; and
filling the trench ring with a conductive material to form a seal ring.

### Claim 10 (depends on 9)

The method of claim 9, wherein the trench ring is a full ring.

### Claim 11 (depends on 9)

The method of claim 9, wherein the first light-exposure process is performed using a first lithography mask, and the second light-exposure process is performed using a second lithography mask different from the first lithography mask.

### Claim 12 (depends on 11)

The method of claim 11, wherein the first lithography mask and the second lithography mask have different patterns.

### Claim 13 (depends on 11)

The method of claim 11, wherein during the first light-exposure process, the first lithography mask covers the first portion of the photo resist without covering the second portion of the photo resist, and during the second light-exposure process, the second lithography mask covers the second portion of the photo resist without covering the first portion of the photo resist.

### Claim 14 (depends on 9)

The method of claim 9 further comprising forming a first metal line, wherein a first pattern of the first metal line is defined in the first light-exposure process.

### Claim 15 (depends on 14)

The method of claim 14 further comprising forming a second metal line, wherein a second pattern of the second metal line is defined in the second light-exposure process.

### Claim 16

A method comprising:
forming a wafer comprising:
forming a dielectric layer over a semiconductor substrate;
forming a seal ring in the dielectric layer, wherein the seal ring comprises:
a first portion having a first width;
a second portion having a second width; and
a third portion joining the first portion to the second portion, wherein the third portion has a third width greater than the first width and the second width; and
sawing the wafer to form a package comprising the seal ring therein, wherein an edge of the package is parallel to the first portion, the second portion, and the third portion of the seal ring.

### Claim 17 (depends on 16)

The method of claim 16, wherein the forming the seal ring comprises:
forming a photo resist over the dielectric layer;
performing a first light-exposure process on the photo resist to define a first pattern of the first portion of the seal ring;
performing a second light-exposure process on the photo resist to define a second pattern of the second portion of the seal ring;
developing the photo resist to form a patterned photo resist;
etching the dielectric layer to form a trench, wherein the etching is performed using the patterned photo resist as an etching mask; and
filling the trench with a conductive material to form a conductive feature.

### Claim 18 (depends on 17)

The method of claim 17, wherein a pattern of the third portion of the seal ring is defined by both of the first light-exposure process and the second light-exposure process.

### Claim 19 (depends on 16)

The method of claim 16, wherein the wafer is an interposer wafer.

### Claim 20 (depends on 1)

The method of claim 1, wherein the seal ring encircles parts of both of the first device region and the second device region.