# US 11,444,037 B2 · Semiconductor devices having crack-inhibiting structures

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- Number: US 11,444,037 B2
- Document ID: US11444037B2
- Status: Granted
- Kind: B2
- Application number: 17/011,799
- Filed: 2020-09-03
- Published: 2020-12-24
- Granted: 2022-09-13
- Earliest claimed: 2018-12-28
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Hyunsuk Chun; Sheng Wei Yang; Shams U. Arifeen
- Web page: https://patentgrep.com/patent/US11444037B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/46: comprising air gaps
- H10W 20/48: Insulating materials thereof
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 70/635: {Through-vias}
- H10W 72/90: Bond pads, in general
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/225: {Bumps having a filler embedded in a matrix}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/253: {not comprising solid metals or solid metalloids, e.g. polymers or ceramics}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9232: {with additional elements interposed between layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 72/981: {Auxiliary members, e.g. spacers}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y02P 80/30: Reducing waste in manufacturing processes; Calculations of released waste quantities
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a bond pad; and
a crack-inhibiting structure positioned beneath and vertically aligned with the bond pad between the bond pad and the substrate, wherein the crack-inhibiting structure includes (a) a metal layer and (b) a barrier member extending at least partially between the metal layer and the bond pad, wherein the bond pad is electrically coupled to the substrate via an electrical path that does not include the crack-inhibiting structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1 wherein the barrier member is a first barrier member, and wherein the crack-inhibiting structure further includes a second barrier member extending at least partially between the metal layer and the bond pad.

### Claim 3 (depends on 2)

The semiconductor device of claim 2 wherein—
the bond pad is configured to be attached to a conductive structure,
when the bond pad is attached to the conductive structure, the first barrier member is positioned outside a footprint of the conductive structure, and
when the bond pad is attached to the conductive structure, the second barrier member is positioned inside a footprint of the conductive structure.

### Claim 4 (depends on 3)

The semiconductor device of claim 3 wherein the first barrier member is a first continuous ring, and wherein the second barrier member is a second continuous ring.

### Claim 5 (depends on 4)

The semiconductor device of claim 4 wherein the first and second continuous rings each have a generally rectangular shape.

### Claim 6 (depends on 3)

The semiconductor device of claim 3 wherein the first barrier member comprises a plurality of spaced apart first columns, and wherein the second barrier member comprises a plurality of spaced apart second columns.

### Claim 7 (depends on 6)

The semiconductor device of claim 6 wherein the first columns are arranged in a first ring, and wherein the second columns are arranged in a second ring.

### Claim 8 (depends on 7)

The semiconductor device of claim 7 wherein the first and second rings each have a generally rectangular shape.

### Claim 9 (depends on 3)

The semiconductor device of claim 3 wherein the first barrier member comprises a plurality of spaced apart first elongate segments, and wherein the second barrier member comprises a plurality of spaced apart second elongate segments.

### Claim 10 (depends on 9)

The semiconductor device of claim 9 wherein the first elongate segments are arranged in a first ring, and wherein the second elongate segments are arranged in a second ring.

### Claim 11 (depends on 10)

The semiconductor device of claim 10 wherein the first and second rings each have a generally rectangular shape.

### Claim 12 (depends on 1)

The semiconductor device of claim 1 wherein the bond pad is exposed from an insulating material, wherein the barrier member extends through the insulating material, and wherein the barrier member is formed from a material that is mechanically stronger than the insulating material.

### Claim 13

A semiconductor device, comprising:
a substrate;
an insulating material over the substrate;
a bond pad; and
a crack-inhibiting structure positioned at least partially in the insulating material beneath and vertically aligned with the bond pad, wherein the crack-inhibiting structure includes a barrier member extending at least partially between the substrate and the bond pad, and wherein the bond pad is electrically coupled to the substrate via an electrical path that does not include the crack-inhibiting structure.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, further comprising a conductive pillar electrically coupled to a portion of the bond pad exposed from the insulating material.

### Claim 15 (depends on 14)

The semiconductor device of claim 14 wherein the barrier member is positioned outside a footprint of the conductive pillar.

### Claim 16 (depends on 14)

The semiconductor device of claim 14 wherein the barrier member is positioned inside a footprint of the conductive pillar.

### Claim 17 (depends on 13)

The semiconductor device of claim 13 wherein the barrier member is a first ring, and wherein the crack-inhibiting structure further includes a second ring, a third ring, and a fourth ring each extending at least partially between the substrate and the bond pad.

### Claim 18 (depends on 17)

The semiconductor device of claim 17 wherein—
the bond pad is configured to be attached to a conductive structure,
when the bond pad is attached to the conductive structure, the first and second rings are positioned outside a footprint of the conductive structure, and
when the bond pad is attached to the conductive structure, the third and fourth rings are positioned inside a footprint of the conductive structure.

### Claim 19 (depends on 17)

The semiconductor device of claim 17 wherein the first, second, third, and fourth rings are each continuous.

### Claim 20 (depends on 17)

The semiconductor device of claim 17 wherein the first, second, third, and fourth rings each comprise a plurality of columns.

### Claim 21 (depends on 17)

The semiconductor device of claim 17 wherein the first, second, third, and fourth rings each comprise a plurality of elongate segments.

### Claim 22

A semiconductor device, comprising:
a substrate;
an insulating material over the substrate;
a plurality of bond pads; and
metal structures, wherein individual ones of the metal structures (a) are positioned and vertically aligned with a corresponding one of the bond pads and between the corresponding one of the bond pads and the substrate and (b) include a barrier member extending at least partially between the substrate and the corresponding one of the bond pads, and wherein the bond pads are electrically coupled to the substrate via electrical paths that do not include the metal structures.