# US 11,444,034 B2 · Redistribution structure for integrated circuit package and method of forming same

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- Number: US 11,444,034 B2
- Document ID: US11444034B2
- Status: Granted
- Kind: B2
- Application number: 17/015,370
- Filed: 2020-09-09
- Published: 2021-11-18
- Granted: 2022-09-13
- Earliest claimed: 2020-05-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chen-Hua Yu; An-Jhih Su; Der-Chyang Yeh; Li-Hsien Huang; Ming Shih Yeh
- Web page: https://patentgrep.com/patent/US11444034B2

## CPC

- H10W 70/614: {the multiple chips being integrally enclosed}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/016: {using moulds}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A redistribution structure for a semiconductor device and a method of forming the same are provided. The semiconductor device includes a die encapsulated by an encapsulant, the die including a pad, and a connector electrically connected to the pad. The semiconductor device further includes a first via in physical contact with the connector. The first via is laterally offset from the connector by a first non-zero distance in a first direction. The first via has a tapered sidewall.

## Claims

### Claim 1

A semiconductor device comprising:
a die encapsulated by an encapsulant, the die comprising a first pad, a second pad, a third pad, and a fourth pad;
a first connector electrically connected to the first pad;
a second connector electrically connected to the second pad;
a third connector electrically connected to the third pad;
a fourth connector electrically connected to the fourth pad;
a first via in physical contact with the first connector, the first via being laterally offset from the first connector by a first non-zero distance in a first direction, the first via having a tapered sidewall;
a second via in physical contact with the second connector, the second via being laterally offset from the second connector by a second non-zero distance in a second direction different from the first direction;
a third via in physical contact with the third connector, the third via being laterally offset from the third connector by a third non-zero distance in a third direction different from the first direction and the second direction; and
a fourth via in physical contact with the fourth connector, the fourth via fully landing on the fourth connector.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a fifth via over and in physical contact with the first via, the fifth via being laterally offset from the first via by a fourth non-zero distance in a fourth direction.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the fourth direction is same as the first direction.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein the fourth direction is opposite to the first direction.

### Claim 5 (depends on 2)

The semiconductor device of claim 2, further comprising a sixth via over and in physical contact with the fifth via, the sixth via being laterally offset from the fifth via by a fifth non-zero distance in a fifth direction opposite to the fourth direction.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a fifth via directly over and in physical contact with the first via.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, further comprising a sixth via directly over and in physical contact with the fifth via.

### Claim 8

A semiconductor device comprising:
a die embedded in an encapsulant, the die comprising a first pad, a second pad, a third pad, and a fourth pad;
a first connector physically connected to the first pad;
a second connector physically connected to the second pad;
a third connector physically connected to the third pad; and
a redistribution structure physically coupled to the first connector, the second connector and the third connector, wherein a first via of the redistribution structure is physically connected to a top surface of the first connector, the first via laterally extending beyond an edge of the first connector in a first direction, the first via having a tapered sidewall, wherein a second via of the redistribution structure is physically connected to a top surface of the second connector, the second via laterally extending beyond an edge of the second connector in a second direction different from the first direction, and wherein a third via of the redistribution structure is physically connected to a top surface of the third connector, the third via laterally extending beyond an edge of the third connector in a third direction different from the first direction and the second direction.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein a fourth via of the redistribution structure is over and physically connected to the first via, a vertical axis of the fourth via being laterally spaced apart from a vertical axis of the first via in a fourth direction, the vertical axis of the first via and the vertical axis of the fourth via being perpendicular to the top surface of the first connector.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein a fifth via of the redistribution structure is over and physically connected to the fourth via, a vertical axis of the fifth via being laterally spaced apart from the vertical axis of the fourth via in a fifth direction opposite to the fourth direction, the vertical axis of the fifth via being perpendicular to the top surface of the first connector.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein a sixth via of the redistribution structure is directly over and physically connected to the fifth via.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, further comprising a fourth connector physically connected to the fourth pad, wherein a fourth via of the redistribution structure is physically connected to a top surface of the fourth connector, the fourth via fully landing on the top surface of the fourth connector.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the first connector, the second connector, and the third connector have a first width, and wherein the fourth connector has a second width greater than the first width.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, further comprising a first conductive column and a second conductive column embedded in the encapsulant, the die being interposed between the first conductive column and the second conductive column.

### Claim 15

A semiconductor device comprising:
a first die embedded in an encapsulant, the first die comprising a first connector and a second connector, wherein a first width of the first connector is greater than a second width of the second connector;
a second die embedded in the encapsulant adjacent the first die, the second die comprising a third connector and a fourth connector; and
a redistribution structure over and electrically coupled to the first die and the second die, wherein a first via of the redistribution structure is in physical contact with a top surface of the first connector and fully overlaps with the first connector in a plan view, wherein a second via of the redistribution structure is in physical contact with a top surface of the second connector and partially overlaps with the second connector in the plan view, the second via being laterally offset from the second connector by a first non-zero distance in a first direction, wherein a third via of the redistribution structure is in physical contact with a top surface of the third connector and partially overlaps with the third connector in the plan view, the third via being laterally offset from the third connector by a second non-zero distance in a second direction different from the first direction, and wherein a fourth via of the redistribution structure is in physical contact with a top surface of the fourth connector and partially overlaps with the fourth connector in the plan view, the fourth via being laterally offset from the fourth connector by a third non-zero distance in a third direction different from the first direction and the second direction.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein a third width of the third connector is equal to the second width of the second connector.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the second direction is opposite to the first direction.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the first non-zero distance is less than or equal to ⅔ of a width of the second via at an interface between the second via and the second connector.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, further comprising a first conductive column and a second conductive column embedded in the encapsulant, the first die and the second die being interposed between the first conductive column and the second conductive column.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein the first non-zero distance is same as the second non-zero distance.