# US 11,444,033 B2 · Hybrid microelectronic substrate and methods for fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,033 B2 - Document ID: US11444033B2 - Status: Granted - Kind: B2 - Application number: 16/918,900 - Filed: 2020-07-01 - Published: 2020-10-22 - Granted: 2022-09-13 - Earliest claimed: 2020-07-01 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Robert Starkston; Robert L. Sankman; Scott M. Mokler; Richard C. Stamey - Web page: https://patentgrep.com/patent/US11444033B2 ## CPC - H10W 70/611: {for connecting multiple chips together} - H10P 72/74: {using temporarily an auxiliary support} - H10W 70/095: {of vias therein} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers} - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 70/686: {the multiple insulating layers having different compositions, e.g. polymer layer on glass substrate} - H10W 70/69: Insulating materials thereof - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10W 90/00: Package configurations - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required. ## Claims ### Claim 1 A method of forming a hybrid microelectronic substrate, comprising: forming a high density microelectronic patch substrate having a first surface, an opposing second surface, and at least one side, wherein the high density microelectronic patch substrate comprises a plurality of dielectric layers and a plurality of conductive routes; aligning the first surface of the high density microelectronic patch substrate on a panel; disposing a first dielectric material layer over the high density microelectronic patch substrate, wherein the first dielectric material layer contacts at least one dielectric layer of the plurality of dielectric layer of the high density microelectronic patch substrate at the second surface thereof and contacts the at least one side of the high density microelectronic patch substrate; forming at least one additional dielectric material layer over the first dielectric material layer; forming at least one conductive route within the first dielectric material layer and the at least one additional dielectric material layer, wherein the first dielectric material, the at least one additional dielectric material layer, and the at least one conductive route within the first dielectric layer and the at least one addition dielectric material comprise a lower density microelectronic substrate and wherein the lower density microelectronic substrate includes at least one contact pad formed in or on an outer surface of an uppermost dielectric material layer of the at least one additional dielectric material layer, and wherein the at least one top contact pad is in electrical contact with at least one conductive route of the plurality of conductive routes within the lower density microelectronic substrate; and forming at least one electrical contact through a portion of the first dielectric material layer to electrical connect the at least one conductive route of the lower density microelectronic substrate to the high density microelectronic patch substrate. ### Claim 2 (depends on 1) The method of claim 1, wherein forming at least one electrical contact through a portion of the first dielectric material layer to electrical connect the at least one conductive route of the lower density microelectronic substrate to the high density microelectronic patch substrate comprises forming at least one conductive microvia through a portion of the first dielectric material layer prior to forming the at least one additional dielectric material layer. ### Claim 3 (depends on 2) The method of claim 2, wherein forming the at least one conductive microvia through a portion of the first dielectric material layer comprises forming at least one via with a laser and filling the at least one via with a conductive material. ### Claim 4 (depends on 1) The method of claim 1, wherein forming at least one electrical contact through a portion of the first dielectric material layer to electrical connect the at least one conductive route of the lower density microelectronic substrate to the high density microelectronic patch substrate comprises forming a conductive blind via through the at least one additional dielectric material layer and through a portion of the first dielectric material. ### Claim 5 (depends on 4) The method of claim 4, wherein forming a conductive blind via through the at least one additional dielectric material layer and through a portion of the first dielectric material comprises forming a via through the at least one additional dielectric material layer and through a portion of the first dielectric material and plating a conductive material in the via. ### Claim 6 (depends on 1) The method of claim 1, wherein forming at least one additional dielectric material layer over the first dielectric material layer comprises forming at least one additional dielectric material layer over the first dielectric material layer, wherein the at least one additional dielectric material layer is a different dielectric material from the first dielectric material layer. ### Claim 7 (depends on 1) The method of claim 1, wherein forming the high density microelectronic patch substrate further includes forming a plurality of bond pads in or on the first surface of the high density microelectronic patch substrate and forming a plurality of bond pads in or on the second surface of the high density microelectronic patch substrate; and, wherein at least one conductive route of the plurality of conductive routes within the high density microelectronic patch substrate extends between one of the plurality of bond pads in or on the first surface of the high density microelectronic patch substrate and one of the plurality of bond pads in or on the second surface of the high density microelectronic patch substrate. ### Claim 8 (depends on 1) The method of claim 1, wherein the plurality of dielectric material layers of the high density microelectronic patch substrate is a different dielectric material from the first dielectric material layer and the additional dielectric material layers of the lower density microelectronic substrate. ### Claim 9 (depends on 1) The method of claim 1, further including forming at least one top contact pad on the panel, wherein disposing the first dielectric material layer over the high density microelectronic patch substrate encases the at least one top contact pad, and wherein the at least one top contact pad is in electrical contact with at least one conductive route of the plurality of conductive routes within the lower density microelectronic substrate. ### Claim 10 (depends on 1) The method of claim 1, wherein the plurality of conductive routes of the high density microelectronic patch substrate comprise a plurality of conductive traces formed in or on each dielectric material layer of the plurality of dielectric layers, and wherein the conductive traces are connected with a plurality of conductive vias extending through each dielectric layer of the plurality of dielectric layers. ### Claim 11 An electronic system, comprising: a board; and a microelectronic component attached to the board, wherein at least one of the microelectronic component and the board, includes a hybrid microelectronic substrate, comprising: a high density microelectronic patch substrate having a first surface, an opposing second surface, and at least one side, wherein the high density microelectronic patch substrate comprises a plurality of dielectric layers and a plurality of conductive routes; and a lower density microelectronic substrate, wherein the high density patch substrate is embedded within a first dielectric layer of the lower density microelectronic substrate, wherein a first dielectric material layer of the lower density microelectronic substrate contacts at least one dielectric layer of the plurality of dielectric layers of the high density microelectronic patch substrate at the second surface thereof and contacts the at least one side of the high density microelectronic patch substrate, wherein at least one conductive route of a plurality of conductive routes within the lower density microelectronic substrate is in electrical contact with at least one conductive route of the plurality of conductive routes within the high density microelectronic patch substrate at the high density microelectronic patch substrate second surface, wherein the lower density microelectronic substrate includes at least one top contact pad formed in the first dielectric material layer, and wherein the at least one top contact pad is in electrical contact with at least one conductive route of the plurality of conductive routes within the lower density microelectronic substrate. ### Claim 12 (depends on 11) The electronic system of claim 11, wherein at least one conductive route of the plurality of conductive routes within the lower density microelectronic substrate is in electrical contact with at least one conductive route of a plurality of conductive routes within the high density microelectronic patch substrate through a microvia extending through a portion the first dielectric material layer. ### Claim 13 (depends on 11) The electronic system of claim 11, wherein the lower density microelectronic substrate includes a plurality of additional dielectric material layers formed on the first dielectric material layer. ### Claim 14 (depends on 13) The electronic system of claim 13, wherein the plurality of additional dielectric material layers of the lower density microelectronic substrate comprises a different dielectric material from the first dielectric material layer of the lower density microelectronic substrate. ### Claim 15 (depends on 13) The electronic system of claim 13, wherein at least one conductive route of the plurality of conductive routes within the lower density microelectronic substrate is in electrical contact with at least one conductive route of the plurality of conductive routes within the high density microelectronic patch substrate through a conductive blind via extending through the plurality of additional dielectric material layers and through a portion of first dielectric material layer. ### Claim 16 (depends on 13) The electronic system of claim 13, wherein the lower density microelectronic substrate includes at least one contact pad formed in or on an outer surface of an uppermost dielectric material layer of the plurality of additional dielectric material layers. ### Claim 17 (depends on 11) The electronic system of claim 11, wherein the high density microelectronic patch substrate further includes a plurality of bond pads in or on the first surface of the high density microelectronic patch substrate and a plurality of bond pads in or on the second surface of the high density microelectronic patch substrate; and, wherein at least one conductive route of the plurality of conductive routes within the high density microelectronic patch substrate extends between one of the plurality of bond pads in or on the first surface of the high density microelectronic patch substrate and one of the plurality of bond pads in or on the second surface of the high density microelectronic patch substrate. ### Claim 18 (depends on 11) The electronic system of claim 11, wherein the lower density microelectronic substrate includes a plurality of additional dielectric material layers formed on the first dielectric material layer, and wherein the plurality of dielectric material layers of the high density microelectronic patch substrate is a different dielectric material from the first dielectric material layer and the additional dielectric material layers of the lower density microelectronic substrate. ### Claim 19 (depends on 11) The electronic system of claim 11, wherein the plurality of conductive routes of the high density microelectronic patch substrate comprise a plurality of conductive traces formed in or on each dielectric material layer of the plurality of dielectric layers, and wherein the conductive traces are connected with a plurality of conductive vias extending through each dielectric layer of the plurality of dielectric layers.