# US 11,444,032 B2 · Semiconductor package device and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,032 B2 - Document ID: US11444032B2 - Status: Granted - Kind: B2 - Application number: 16/917,335 - Filed: 2020-06-30 - Published: 2021-12-30 - Granted: 2022-09-13 - Earliest claimed: 2020-06-30 - Assignees: Advanced Semiconductor Engineering, Inc. - Applicants: Advanced Semiconductor Engineering, Inc. - Inventors: Yencheng Kuo; Shao-Lun Yang - Web page: https://patentgrep.com/patent/US11444032B2 ## CPC - B81B 7/0061: {suitable for fluid transfer from the MEMS out of the package or vice versa, e.g. transfer of liquid, gas, sound} - H10W 70/611: {for connecting multiple chips together} - B81B 7/0074: {3D packaging, i.e. encapsulation containing one or several MEMS devices arranged in planes non-parallel to the mounting board} - H10W 70/095: {of vias therein} - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/50: Bond wires - H10W 90/00: Package configurations - B81B 2201/0214: Biosensors; Chemical sensors - B81B 2201/0257: Microphones or microspeakers - B81B 2201/0264: Pressure sensors - B81B 2201/0278: Temperature sensors - B81B 2207/012: the micromechanical device and the control or processing electronics being separate parts in the same package - B81B 2207/07: Interconnects - B81C 2203/0792: Forming interconnections between the electronic processing unit and the micromechanical structure - H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage} - H10W 72/0198: {batch processes} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01) ## Abstract A semiconductor package device and a method of manufacturing a semiconductor package device are provided. The semiconductor package device includes a substrate, a first electronic component, a first dielectric layer, and a first hole. The substrate has a first surface and a second surface opposite to the first surface. The first electronic component is disposed on the first surface. The first dielectric layer is disposed on the second surface and has a third surface away from the substrate. The first hole extends from the first dielectric layer and the substrate. The first hole is substantially aligned with the first electronic component. ## Claims ### Claim 1 A semiconductor package device, comprising: a substrate having a first surface and a second surface opposite to the first surface; a first electronic component disposed on the first surface; a first dielectric layer disposed on the second surface and having a third surface away from the substrate; a first hole extending through the first dielectric layer and the substrate; and a plurality of through vias in the first dielectric layer, wherein the plurality of through vias are electrically connected to the substrate, wherein the first hole is substantially aligned with the first electronic component. ### Claim 2 (depends on 1) The semiconductor package device of claim 1, further comprising: a second electronic component disposed on the first surface; and a second hole extending from the third surface to the first surface, wherein the second hole is substantially aligned with the second electronic component. ### Claim 3 (depends on 1) The semiconductor package device of claim 1, the first hole having two ends, one end is adjacent to a lateral surface of the first dielectric layer and the other end is adjacent to the first surface. ### Claim 4 (depends on 1) The semiconductor package device of claim 1, further comprising a second dielectric layer disposed on the first surface, wherein the first electronic component is covered by the second dielectric layer. ### Claim 5 (depends on 1) The semiconductor package device of claim 1, further comprising a semiconductor die electrically connected to the substrate through a bonding wire, wherein the semiconductor die and the bonding wire are covered by the first dielectric layer. ### Claim 6 (depends on 1) The semiconductor package device of claim 1, further comprising a reflection layer disposed along a sidewall of the first hole. ### Claim 7 (depends on 1) The semiconductor package device of claim 1, wherein the first hole has a tapered profile. ### Claim 8 (depends on 1) The semiconductor package device of claim 1, wherein the first hole has a sidewall substantially perpendicular to the third surface. ### Claim 9 (depends on 1) The semiconductor package device of claim 1, wherein the first electronic component is a microelectromechanical systems (MEMS) device. ### Claim 10 A method of manufacturing a semiconductor package device, comprising: providing a substrate having a first surface and a second surface opposite to the first surface; forming a first dielectric layer on the second surface and the first dielectric layer having a third surface away from the substrate; forming a first hole extending from the third surface to the first surface; and disposing a first electronic component on the first surface, wherein the first hole is substantially aligned with the first electronic component. ### Claim 11 (depends on 10) The method of claim 10, further comprising: forming a second hole having two ends, one end is adjacent to a lateral surface of the first dielectric layer and the other end is adjacent to the first surface. ### Claim 12 (depends on 10) The method of claim 10, wherein forming the first hole includes removing a portion of the first dielectric layer and the substrate by laser ablation. ### Claim 13 (depends on 10) The method of claim 10, further comprising: prior to forming the first hole, forming a second hole extending from the first surface to the second surface; and disposing a second electronic component on the second surface to align with a second hole.