# US 11,444,031 B2 · Semiconductor device with transistor local interconnects

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- Number: US 11,444,031 B2
- Document ID: US11444031B2
- Status: Granted
- Kind: B2
- Application number: 17/039,187
- Filed: 2020-09-30
- Published: 2021-01-14
- Granted: 2022-09-13
- Earliest claimed: 2011-12-13
- Assignees: GlobalFoundries U.S. Inc.
- Applicants: GLOBALFOUNDRIES U.S. Inc.
- Inventors: Mahbub Rashed; Irene Y. Lin; Steven Soss; Jeff Kim; Chinh Nguyen; Marc Tarabbia; Scott Johnson; Subramani Kengeri; Suresh Venkatesan
- Web page: https://patentgrep.com/patent/US11444031B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 89/10: Integrated device layouts
- H10W 20/0698: {Local interconnections}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10D 84/907: {CMOS gate arrays}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers. The first CB layer is electrically connected adjacent the first end of the CA layer and the second layer is electrically connected adjacent the second end of the CA layer. The first CB layer, the second CB layer and the CA layer are disposed between a first metal layer and the semiconductor substrate. The first metal layer being disposed above each source, each drain, and each gate of the first and second transistors. The CA layer extends substantially parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers. At least one via selectively provides an electrical connection between the CA or CB layers and the at least one metal layer.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate;
a first transistor and a second transistor formed on the semiconductor substrate, wherein each transistor comprises a source, a drain, and a gate, wherein the gate of the first transistor extends longitudinally as part of a first linear strip and wherein the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip;
a first CB layer forming a local interconnect layer electrically connected to the gate of the first transistor;
a second CB layer forming a local interconnect layer electrically connected to the gate of the second transistor;
a CA layer forming a local interconnect layer extending longitudinally between a first end and a second end of the CA layer, wherein the CA layer is electrically connected to the first and second CB layers;
wherein the first CB layer is electrically connected adjacent the first end of the CA layer and the second layer is electrically connected adjacent the second end of the CA layer,
wherein the first CB layer, the second CB layer and the CA layer are disposed between a first metal layer and the semiconductor substrate, the first metal layer being disposed above each source, each drain, and each gate of the first and second transistors, and
wherein the CA layer extends substantially parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers; and
at least one via selectively providing an electrical connection between the CA or CB layers and the at least one metal layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the at least one via selectively provides an electrical connection between the CA layer and the at least one metal layer.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein the at least one metal layer is the first metal layer.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the at least one via selectively provides an electrical connection between one of the CB layers and the at least one metal layer.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein the at least one metal layer is the first metal layer.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the at least one via and the CA layer are formed of substantially different materials.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein the at least one via includes copper and the CA layer includes tungsten.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the CA layer is disposed between the gate of the first transistor and the gate of the second transistor.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, wherein the CA layer extends substantially parallel to the first linear strip and the second linear strip.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, further comprising a third transistor having a gate extending longitudinally along the first linear strip and a fourth transistor having a gate extending longitudinally along the second linear strip.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10, wherein the gate of the first transistor and the gate of the third transistor are separated by a gap, and wherein the gate of the second transistor and the gate of fourth transistor are separated by a gap.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11, wherein the CA layer, the first CB layer, and the second CB layer each terminate at an uppermost surface, and wherein the uppermost surface of the CA layer, the uppermost surface of the first CB layer, and the uppermost surface of the second CB layer are at a height above the semiconductor substrate.

### Claim 13 (depends on 1)

The semiconductor device according to claim 1 wherein the first CB layer and the second CB layer each have a height of about 70 nm.