# US 11,444,030 B2 · Semiconductor device and method of forming the same

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- Number: US 11,444,030 B2
- Document ID: US11444030B2
- Status: Granted
- Kind: B2
- Application number: 16/691,869
- Filed: 2019-11-22
- Published: 2021-05-27
- Granted: 2022-09-13
- Earliest claimed: 2019-11-22
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Inventors: Hyunwoo Yang; Naganivetha Thiyagarajah; De Wei Shawn Wong; Suk Hee Jang
- Web page: https://patentgrep.com/patent/US11444030B2

## CPC

- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10B 53/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B 53/30: characterised by the memory core region
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/42: Vias, e.g. via plugs
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A semiconductor device may be provided, including a first dielectric layer having a first region and a second region laterally adjacent to the first region. The semiconductor device may further include a bottom electrode at least partially arranged within the first region of the first dielectric layer, a memory element arranged over the bottom electrode, a top electrode arranged over the memory element, and a second dielectric layer arranged over at least the first region of the first dielectric layer. The second dielectric layer may surround the memory element and may surround at least a part of the top electrode. The semiconductor device may further include a third dielectric layer arranged over the second region of the first dielectric layer and laterally adjacent to the second dielectric layer, and a conductive interconnect arranged in the third dielectric layer and the second region of the first dielectric layer.

## Claims

### Claim 1

A semiconductor device comprising:
a first dielectric layer having a first region and a second region laterally adjacent to the first region;
a bottom electrode at least partially arranged within the first region of the first dielectric layer;
a memory element arranged over the bottom electrode;
a top electrode arranged over the memory element;
a second dielectric layer arranged over at least the first region of the first dielectric layer, the second dielectric layer surrounding the memory element and surrounding at least a part of the top electrode;
a third dielectric layer arranged over the second region of the first dielectric layer and laterally adjacent to the second dielectric layer, wherein the third dielectric layer is in physical contact with a top surface of the first dielectric layer;
a conductive interconnect arranged in the third dielectric layer and the second region of the first dielectric layer; and
a metal layer covering the top electrode, the second dielectric layer, the third dielectric layer, and the conductive interconnect,
wherein the second dielectric layer is in physical contact with a side surface of the memory element and a side surface of the top electrode, and wherein the second dielectric layer is in physical contact with an entire side surface of the third dielectric layer; and
wherein the metal layer extends across the first region and the second region and is in physical contact with the top electrode, the second dielectric layer, the third dielectric layer, and the conductive interconnect.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a top surface of the second dielectric layer is co-planar with a top surface of the third dielectric layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the second dielectric layer is in physical contact with the top surface of the first dielectric layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the second dielectric layer is surrounding at least one third of a height of the top electrode.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second dielectric layer is arranged over at least a part of the bottom electrode.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the first dielectric layer comprises at least one of tetraethoxysilane (TEOS), SiCOH, SiN, SiCN, SiO2, or combinations thereof.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the second dielectric layer comprises at least one of SiN, SiOyNz, AlOyNz, TiOyNz, SiCyNz, MgO, or combinations thereof, wherein 0≤y≤1 and 0≤z≤1.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the third dielectric layer comprises at least one of SiO2, TEOS, SiCOH, or combinations thereof.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, further comprising:
a dielectric blocking layer arranged under the first dielectric layer, wherein the bottom electrode and the conductive interconnect extend through the dielectric blocking layer.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further comprising:
a further bottom electrode at least partially arranged within the first region of the first dielectric layer;
a further memory element arranged over the further bottom electrode;
a further top electrode arranged over the further memory element;
wherein the second dielectric layer is arranged surrounding the further memory element and surrounding at least a part of the further top electrode;
wherein the second dielectric layer is arranged to fill an entire space between the memory element and the further memory element and to at least partially fill a space between the top electrode and the further top electrode.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the memory element comprises a magnetoresistive random access memory, a phase change random access memory, a resistive random access memory, or a ferroelectric random access memory.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein the second dielectric layer is arranged to fill an entire space between the memory element and the third dielectric layer.

### Claim 13

A method of forming a semiconductor device, the method comprising:
providing a first dielectric layer having a first region and a second region laterally adjacent to the first region;
forming a bottom electrode at least partially within the first region of the first dielectric layer;
forming a memory element over the bottom electrode;
forming a top electrode over the memory element;
forming a second dielectric layer over at least the first region of the first dielectric layer, the second dielectric layer surrounding the memory element and surrounding at least a part of the top electrode;
forming a third dielectric layer over the second region of the first dielectric layer and laterally adjacent to the second dielectric layer, wherein the third dielectric layer is in physical contact with a top surface of the first dielectric layer;
forming a conductive interconnect in the third dielectric layer and the second region of the first dielectric layer; and
forming a metal layer covering the top electrode, the second dielectric layer, the third dielectric layer, and the conductive interconnect,
wherein the second dielectric layer is in physical contact with a side surface of the memory element and a side surface of the top electrode, and wherein the second dielectric layer is in physical contact with an entire side surface of the third dielectric layer; and
wherein the metal layer extends across the first region and the second region and is in physical contact with the top electrode, the second dielectric layer, the third dielectric laver, and the conductive interconnect.

### Claim 14 (depends on 13)

The method of claim 13, further comprising forming the second dielectric layer and the third dielectric layer such that a top surface of the second dielectric layer is co-planar with a top surface of the third dielectric layer.

### Claim 15 (depends on 13)

The method of claim 13, wherein forming the second dielectric layer further comprises:
forming an initial second dielectric layer over the first region and the second region of the first dielectric layer,
configuring a portion of the initial second dielectric layer over the first region to form the second dielectric layer surrounding the memory element and surrounding at least a part of the top electrode, and
configuring the initial second dielectric layer over the second region to expose the second region of the first dielectric layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the initial second dielectric layer further comprises forming the initial second dielectric layer over the bottom electrode, the memory element, and the top electrode with a step coverage larger than 80%.

### Claim 17 (depends on 15)

The method of claim 15, wherein forming the initial second dielectric layer further comprises forming the initial second dielectric layer with a thickness substantially larger than a spacing between the memory element and an adjacent memory element.

### Claim 18 (depends on 15)

The method of claim 15, wherein forming the initial second dielectric layer further comprises forming the initial second dielectric layer via cyclic or pulse mode deposition.