# US 11,444,029 B2 · Back-end-of-line interconnect structures with varying aspect ratios

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- Number: US 11,444,029 B2
- Document ID: US11444029B2
- Status: Granted
- Kind: B2
- Application number: 16/799,048
- Filed: 2020-02-24
- Published: 2021-08-26
- Granted: 2022-09-13
- Earliest claimed: 2020-02-24
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Prasad Bhosale; Nicholas Anthony Lanzillo; Michael Rizzolo; Chih-Chao Yang
- Web page: https://patentgrep.com/patent/US11444029B2

## CPC

- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/031: {of conductive parts of the interconnections}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/4437: {the principal metal being a transition metal}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes an interlayer dielectric layer, a first set of back-end-of-line interconnect structures disposed in the interlayer dielectric layer, and a second set of back-end-of-line interconnect structures at least partially disposed in the interlayer dielectric layer. Each of the first set of back-end-of-line interconnect structures has a first width and a first height providing a first aspect ratio. Each of the second set of back-end-of-line interconnect structures has a second width and a second height providing a second aspect ratio different than the first aspect ratio. The second width is greater than the first width, and the second height is different than the first height.

## Claims

### Claim 1

A semiconductor structure, comprising:
an interlayer dielectric layer;
a first set of back-end-of-line interconnect structures disposed in the interlayer dielectric layer; and
a second set of back-end-of-line interconnect structures at least partially disposed in the interlayer dielectric layer;
wherein each of the first set of back-end-of-line interconnect structures has a first aspect ratio, the first aspect ratio being defined by a first width at a bottom surface of each of the first set of back-end-of-line interconnect structures and a first height measured from a top surface of each of the first set of back-end-of-line interconnect structures to the bottom surface of each of the first set of back-end-of-line interconnect structures;
wherein each of the second set of back-end-of-line interconnect structures has a second aspect ratio different than the first aspect ratio, the second aspect ratio being defined by a second width at a bottom surface of each of the second set of back-end-of-line interconnect structures and a second height measured from a top surface of each of the second set of back-end-of-line interconnect structures to the bottom surface of each of the second set of back-end-of-line interconnect structures;
wherein the second width is greater than the first width and the second height is greater than the first height;
wherein sidewalls of each of the first set of back-end-of-line interconnect structures have a first constant sidewall taper angle such that the first width at the bottom surface of each of the first set of back-end-of-line interconnect structures is less than a third width at the top surface of each of the first set of back-end-of-line interconnect structures; and
wherein sidewalls of each of the second set of back-end-of-line interconnect structures have a second constant sidewall taper angle such that the second width at the bottom surface of each of the second set of back-end-of-line interconnect structures is less than a fourth width at the top surface of each of the second set of back-end-of-line interconnect structures.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the first set of back-end-of-line interconnect structures and the second set of back-end-of-line interconnect structures comprise a given metal material.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the given metal material comprises cobalt (Co).

### Claim 4 (depends on 2)

The semiconductor structure of claim 2, wherein the second height is about twice the first height, and wherein the second width is about three times the first width or greater.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the second set of back-end-of-line interconnect structures is fully disposed in the interlayer dielectric layer.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the second height is a function of a line resistance target for the second set of back-end-of-line interconnect structures.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, wherein the line resistance target for the second set of back-end-of-line interconnect structures is based at least in part on one or more device performance requirements.

### Claim 8

An integrated circuit comprising:
a semiconductor structure comprising:
an interlayer dielectric layer;
a first set of back-end-of-line interconnect structures disposed in the interlayer dielectric layer; and
a second set of back-end-of-line interconnect structures at least partially disposed in the interlayer dielectric layer;
wherein each of the first set of back-end-of-line interconnect structures has a first aspect ratio, the first aspect ratio being defined by a first width at a bottom surface of each of the first set of back-end-of-line interconnect structures and a first height measured from a top surface of each of the first set of back-end-of-line interconnect structures to the bottom surface of each of the first set of back-end-of-line interconnect structures;
wherein each of the second set of back-end-of-line interconnect structures has a second aspect ratio different than the first aspect ratio, the second aspect ratio being defined by a second width at a bottom surface of each of the second set of back-end-of-line interconnect structures and a second height measured from a top surface of each of the second set of back-end-of-line interconnect structures to the bottom surface of each of the second set of back-end-of-line interconnect structures;
wherein the second width is greater than the first width and the second height is greater than the first height;
wherein sidewalls of each of the first set of back-end-of-line interconnect structures have a first constant sidewall taper angle such that the first width at the bottom surface of each of the first set of back-end-of-line interconnect structures is less than a third width at the top surface of each of the first set of back-end-of-line interconnect structures; and
wherein sidewalls of each of the second set of back-end-of-line interconnect structures have a second constant sidewall taper angle such that the second width at the bottom surface of each of the second set of back-end-of-line interconnect structures is less than a fourth width at the top surface of each of the second set of back-end-of-line interconnect structures.

### Claim 9 (depends on 8)

The integrated circuit of claim 8, wherein the first set of back-end-of-line interconnect structures and the second set of back-end-of-line interconnect structures comprise cobalt (Co).

### Claim 10 (depends on 8)

The integrated circuit of claim 8, wherein the second height is a function of a line resistance target for the second set of back-end-of-line interconnect structures.

### Claim 11 (depends on 10)

The integrated circuit of claim 10, wherein the line resistance target for the second set of back-end-of-line interconnect structures is based at least in part on one or more device performance requirements.

### Claim 12 (depends on 8)

The integrated circuit of claim 8, wherein the second set of back-end-of-line interconnect structures is fully disposed in the interlayer dielectric layer.

### Claim 13 (depends on 8)

The integrated circuit of claim 8, wherein the second height is about twice the first height, and wherein the second width is about three times the first width or greater.