# US 11,444,025 B2 · Transistor and fabrication method thereof

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- Number: US 11,444,025 B2
- Document ID: US11444025B2
- Status: Granted
- Kind: B2
- Application number: 17/156,648
- Filed: 2021-01-25
- Published: 2021-12-23
- Granted: 2022-09-13
- Earliest claimed: 2020-06-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hung-Wei Li; Yu-Ming Lin; Mauricio Manfrini; Sai-Hooi Yeong
- Web page: https://patentgrep.com/patent/US11444025B2

## CPC

- H10W 20/42: Vias, e.g. via plugs
- H10B 51/10: characterised by the top-view layout
- H10B 51/30: characterised by the memory core region
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 64/689: {having ferroelectric layers}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/48: Insulating materials thereof
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A transistor includes a gate, a channel layer, a gate insulation layer, a passivation layer, a liner, a first signal line, and a second signal line. The first signal line is embedded in the passivation layer to form a first via in the passivation layer and overlapping the channel layer. The second signal line is embedded in the passivation layer to form a second via in the passivation layer overlapping the channel layer. The second signal line is in contact with the channel layer. The liner includes an insulation region and a conductive region connected with the insulation region. The insulation region is disposed over the passivation layer and on sidewalls of the first via. The conductive region is disposed under a bottom of the first via and connected with the channel layer. The first signal line is electrically connected with the channel layer through the conductive region.

## Claims

### Claim 1

A fabrication method of a transistor, comprising:
forming a gate and a word line electrically connected with the gate over a substrate;
forming a gate insulation layer over the gate;
forming a channel layer over the gate insulation layer;
forming a passivation layer over the gate insulation layer, wherein the passivation layer has a first opening overlapped with the channel layer;
forming a metal layer on the passivation layer and in the first opening;
forming a second opening penetrating through the passivation layer and the metal layer, wherein the second opening is overlapping the channel layer;
heating the metal layer to form a liner comprising:
an insulation region, disposed over the passivation layer and sidewalls of the first opening; and
a conductive region, disposed in a bottom of the first opening and connected with the channel layer;
forming a first signal line in the first opening; and
forming a second signal line in the second opening.

### Claim 2 (depends on 1)

The fabrication method according to claim 1, wherein the metal layer includes Al.

### Claim 3 (depends on 1)

The fabrication method according to claim 1, wherein the insulation region includes Al2O3, and the conductive region includes AlOx, InOy, and ZnOz, wherein x is not 3/2, and x, y, and z are greater than 0.

### Claim 4 (depends on 1)

The fabrication method according to claim 1, wherein the channel layer includes indium gallium zinc oxide.

### Claim 5

A fabrication method of a transistor, comprising:
forming a gate and a word line electrically connected with the gate over a substrate;
forming a gate insulation layer over the gate;
forming a channel layer over the gate insulation layer;
forming a second signal line in contact with the channel layer;
forming a first passivation layer over the gate insulation layer, wherein the second signal line is disposed in a second opening of the first passivation layer;
forming a first opening penetrating through the first passivation layer and overlapped with the channel layer;
forming a second passivation layer containing hydrogen in the first opening, wherein the second passivation layer is in contact with the channel layer;
forming an n-type doped region at the junction between the channel layer and the second passivation layer;
forming a third opening penetrating through the second passivation layer; and
forming a first signal line in contact with the n-type doped region under the third opening.

### Claim 6 (depends on 5)

The fabrication method according to claim 5, further comprises
forming a liner on the second signal line and the channel layer; and
forming the first opening penetrating through the first passivation layer and the liner.

### Claim 7 (depends on 6)

The fabrication method according to claim 6, wherein the liner includes Al2O3.

### Claim 8 (depends on 5)

The fabrication method according to claim 5, wherein the channel layer includes indium gallium zinc oxide.

### Claim 9 (depends on 5)

The fabrication method according to claim 5, wherein a material of the first signal line is different from a material of the second signal line.

### Claim 10 (depends on 9)

The fabrication method according to claim 9, wherein a work function of the first signal line is lower than a work function of the second signal line.

### Claim 11 (depends on 5)

The fabrication method according to claim 5, wherein a distance between the first signal line and the second signal line is longer than a distance between the second passivation layer and the second signal line.

### Claim 12 (depends on 5)

The fabrication method according to claim 5, further comprises
forming a dielectric layer over a substrate, wherein the gate is embedded in the dielectric layer; and
forming the gate insulation layer over the dielectric layer and the gate.

### Claim 13 (depends on 5)

The fabrication method according to claim 5, wherein Schottky contact is between the first signal line and the channel layer, and Ohmic contact is between the second signal line and the channel layer.