# US 11,444,024 B2 · Subtractively patterned interconnect structures for integrated circuits

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- Number: US 11,444,024 B2
- Document ID: US11444024B2
- Status: Granted
- Kind: B2
- Application number: 17/087,519
- Filed: 2020-11-02
- Published: 2022-05-05
- Granted: 2022-09-13
- Earliest claimed: 2020-11-02
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Kevin Lin; Noriyuki Sato; Tristan Tronic; Michael Christenson; Christopher Jezewski; Jiun-Ruey Chen; James M. Blackwell; Matthew Metz; Miriam Reshotko; Nafees Kabir; Jeffery Bielefeld; Manish Chandhok; Hui Jae Yoo; Elijah Karpov; Carl Naylor; Ramanan Chebiam
- Web page: https://patentgrep.com/patent/US11444024B2

## CPC

- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/42: Vias, e.g. via plugs
- H10P 50/71: {using masks for conductive or resistive materials}
- H10W 20/032: {of conductive barrier, adhesion or liner layers}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/039: {also covering sidewalls of the conductive structures}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/092: {by smoothing the dielectric parts}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/46: comprising air gaps
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10W 20/0375: {comprising multiple stacked thin barrier, adhesion or liner layers not being formed in openings in dielectrics}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

## Claims

### Claim 1

An integrated circuit (IC) structure, comprising:
a substrate comprising a plurality of transistors; and
an interconnect structure coupled to the transistors, wherein the interconnect structure comprises:
rows of first interconnect features, wherein a first end space between an adjacent pair of the first interconnect features has a first misregistration in a first lateral dimension relative to an underlying feature of the IC structure; and
rows of second interconnect features co-planar with the first interconnect features, wherein:
individual ones of the rows of second interconnect features are between, and parallel with, individual ones of the rows of first interconnect features; and
a second end space between an adjacent pair of the second interconnect features has a second misregistration in the first lateral dimension relative to the underlying feature of the IC structure;
a dielectric material layer between the first and second interconnect features;
a first cap material over the first interconnect features, wherein the first cap material has a first composition;
a second cap material over the second interconnect features, wherein the second cap material has a second composition, different than the first composition; and
one or more interconnect vias extending through, or comprising, at least one of the first or second cap materials.

### Claim 2 (depends on 1)

The IC structure of claim 1, wherein:
the top width of individual ones of the first interconnect features is smaller than the bottom width of corresponding ones of the first interconnect features;
the top width of individual ones of the second interconnect features is smaller than the bottom width of corresponding ones of the second interconnect features.

### Claim 3 (depends on 1)

The IC structure of claim 1, wherein the first interconnect features comprise a first metal; and
the second interconnect features comprise the first metal.

### Claim 4 (depends on 1)

The IC structure of claim 1, wherein the first composition comprises a first dielectric material and the second composition comprises a second dielectric material.

### Claim 5 (depends on 4)

The IC structure of claim 4, wherein the first interconnect features are first interconnect lines, the second interconnect features are second interconnect lines; and
wherein the one or more interconnect vias further comprises:
a first via over, and in physical contact with, one of the first interconnect lines, wherein the first via extends through the first cap material; and
a second via over, and in physical contact with, one of the second interconnect lines, wherein the second via extends through the second cap material.

### Claim 6 (depends on 5)

The IC structure of claim 5, wherein the first via has a third misregistration in the first lateral dimension relative to the underlying structure of the substrate, and wherein the second via has a fourth misregistration in the first lateral dimension relative to the underlying structure of the substrate.

### Claim 7 (depends on 3)

The IC structure of claim 3, wherein the first composition comprises a second metal, different than the first metal, and the second composition comprises a third metal, different than the first and second metals.

### Claim 8 (depends on 3)

The IC structure of claim 3, wherein the first metal is at least one of Ru, Co, Mo, W, Ir, Rh, Pt or Cu.

### Claim 9 (depends on 1)

The IC structure of claim 1, wherein individual ones of the first interconnect features comprise first interconnect lines and the interconnect vias comprise a first interconnect via over, and in contact with, one of the first interconnect lines, and individual ones of the second interconnect features comprise second interconnect lines and the interconnect vias comprise a second interconnect via over, and in contact with, one of the second interconnect lines.

### Claim 10 (depends on 9)

The IC structure of claim 9, wherein a bottom transverse width of the first or second interconnect via is equal to the top transverse width of an underlying one of the first or second interconnect lines.

### Claim 11 (depends on 9)

The IC structure of claim 9, wherein an interface between the first or second interconnect vias and the underlying one of the first or second interconnect lines is substantially rectangular.

### Claim 12 (depends on 9)

The IC structure of claim 9, wherein the first and second vias comprise a first metal.

### Claim 13 (depends on 11)

The IC structure of claim 11, further comprising an etch stop layer between the interconnect vias and the interconnect lines, wherein the etch stop layer has a different composition than the interconnect vias.

### Claim 14 (depends on 9)

The IC structure of claim 9, wherein the first and second interconnect vias comprise a second metal, different than the first metal.

### Claim 15 (depends on 1)

The IC structure of claim 1, wherein the first interconnect features comprise first interconnect lines and the substrate comprises first vias under the first interconnect lines; and
wherein the one or more interconnect vias further comprise second vias over the first interconnect lines.

### Claim 16 (depends on 15)

The IC structure of claim 15, wherein both the first and second vias comprise a second metal.

### Claim 17 (depends on 15)

The IC structure of claim 15, wherein:
individual ones of the first vias have a top diameter and a bottom diameter; and
the top diameter is smaller than the bottom diameter.

### Claim 18 (depends on 15)

The IC structure of claim 15, wherein the first vias comprise a fill metal and a barrier metal on a sidewall of the fill metal.

### Claim 19 (depends on 18)

The IC structure of claim 18, wherein the barrier metal is absent from sidewalls of the first interconnect lines.

### Claim 20 (depends on 15)

The IC structure of claim 15, wherein the first interconnect lines are over a substrate dielectric material, and wherein at least one of the first vias or second vias extend through the substrate dielectric material and are in contact with an end of one of the first interconnect lines.

### Claim 21 (depends on 1)

The IC structure of claim 1, wherein the first and second interconnect features comprise first and second interconnect lines over a first dielectric material, and wherein a second dielectric material is between a sidewall of the one or more interconnect vias and an adjacent sidewall of the first dielectric material.

### Claim 22 (depends on 1)

The IC structure of claim 1, wherein both the first interconnect features and the second interconnect features have a same misregistration within a second dimension, orthogonal to the first dimension, relative to the underlying feature of the IC structure.

### Claim 23 (depends on 1)

The IC structure of claim 1, further comprising a dielectric material in contact with a sidewall of the first cap material and the first interconnect features, and in contact with a sidewall of the second cap material and the second interconnect features.

### Claim 24 (depends on 1)

The IC structure of claim 1, wherein the first interconnect features are first vias and the second interconnect features are second vias.

### Claim 25 (depends on 1)

A computer platform comprising:
a power supply; and
the IC structure of claim 1 coupled to the power supply.

### Claim 26

A method of forming an integrated circuit (IC) interconnect structure, comprising:
depositing a metal over a substrate;
forming first lines over the metal, wherein the first lines have a first composition;
forming second lines over the metal, and between individual ones of the first lines, wherein the second lines have a second composition, different than the first composition;
segmenting individual ones of the first lines into a plurality of colinear first features;
segmenting individual ones of the second lines into a plurality of colinear second features;
segmenting colinear first interconnect features by removing the metal exposed between adjacent ends of the first features;
segmenting colinear second interconnect features by removing the metal exposed between adjacent ends of the second features;
separating the first interconnect features from the second interconnect features by removing the metal exposed between the first features and the second features;
depositing a dielectric material over the first and second interconnect features; and
forming one or more interconnect vias to at least one of the first or second interconnect features, the interconnect vias extending through, or comprising, at least one of the first or second features.

### Claim 27 (depends on 26)

The method of claim 26, wherein:
adjacent first ends of a pair of the colinear first interconnect features are spaced apart by a first end spacing; and
adjacent second ends of a pair of the colinear second interconnect features are spaced apart by a second end spacing.

### Claim 28 (depends on 27)

The method of claim 27, wherein the first end spacing is laterally offset from the second end spacing and at least one of the first ends is adjacent to a portion of one of the pair of colinear second interconnect features.

### Claim 29 (depends on 26)

The method of claim 26, wherein the segmenting of at least one of the first or second features is subsequent to the separating of the colinear first interconnect features from the colinear second interconnect features.

### Claim 30 (depends on 26)

The method of claim 26, wherein the separating of the colinear first interconnect features from the colinear second interconnect features is subsequent to the segmenting of at least one of the first or second features.