# US 11,444,023 B2 · Semiconductor device, package structure including a heat dissipation element having a conductive base and a plurality of antenna patterns and method of fabricating the semiconductor device

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- Number: US 11,444,023 B2
- Document ID: US11444023B2
- Status: Granted
- Kind: B2
- Application number: 17/079,525
- Filed: 2020-10-26
- Published: 2021-02-11
- Granted: 2022-09-13
- Earliest claimed: 2019-01-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Sen-Kuei Hsu; Hsin-Yu Pan; Yi-Che Chiang
- Web page: https://patentgrep.com/patent/US11444023B2

## CPC

- H10W 20/42: Vias, e.g. via plugs
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 40/10: Arrangements for heating
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/02: of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/685: comprising multiple insulating layers
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 72/90: Bond pads, in general
- H10W 74/01: Manufacture or treatment
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 44/248: {for antennas}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/655: Fan-out layouts
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/9413: {on encapsulations}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, a heat dissipation element and conductive balls. The insulating encapsulant is encapsulating the semiconductor die, and has a first surface and a second surface opposite to the first surface. The first redistribution layer is located on the first surface of the insulating encapsulant and includes at least one feed line and one ground plate. The second redistribution layer is located on the second surface of the insulating encapsulant and electrically connected to the semiconductor die and the first redistribution layer. The heat dissipation element is disposed on the first redistribution layer and includes a conductive base and antenna patterns, wherein the antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer.

## Claims

### Claim 1

A structure, comprising:
a first heat dissipation element comprising a conductive base and a plurality of monopole antenna patterns partially surrounded by and protruding out from the conductive base, and the plurality of monopole antenna patterns is isolated from the conductive base;
a first redistribution layer located over the first heat dissipation element, wherein the first redistribution layer comprises at least one feed line and one ground plate, and the plurality of monopole antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer;
a semiconductor die and an insulating encapsulant located over the first redistribution layer, wherein the insulating encapsulant surrounds the semiconductor die; and
a second heat dissipation element disposed on and electrically connected to the semiconductor die, wherein the insulating encapsulant is located in between the first heat dissipation element and the second heat dissipation element.

### Claim 2 (depends on 1)

The structure according to claim 1, further comprising:
a second redistribution layer located over the insulating encapsulant, wherein the second redistribution layer is electrically connected to the semiconductor die.

### Claim 3 (depends on 1)

The structure according to claim 1, wherein a ratio of a thickness of the first heat dissipation element to a thickness of the insulating encapsulant is in a range of 1:1 to 1:5.

### Claim 4 (depends on 1)

The structure according to claim 1, wherein a ratio of a thickness of the conductive base and a height of the plurality of monopole antenna patterns protruding out from the conductive base is in a range of 1:1.5 to 1:3.

### Claim 5 (depends on 1)

The structure according to claim 1, wherein sidewalls of the conductive base are aligned with sidewalls of the insulating encapsulant.

### Claim 6 (depends on 1)

The structure according to claim 1, wherein a material of the conductive base is the same as a material of the plurality of monopole antenna patterns.

### Claim 7 (depends on 1)

The structure according to claim 1, further comprising a plurality of through insulator vias embedded in the insulating encapsulant and surrounding the semiconductor die, wherein the plurality of through insulator vias is electrically connected to the feed line of the first redistribution layer.

### Claim 8 (depends on 1)

The structure according to claim 1, wherein the second heat dissipation element is electrically connected to the semiconductor die through a plurality of conductive balls.

### Claim 9

A semiconductor device, comprising:
a package structure disposed on a circuit substrate, wherein the package structure comprises:
a semiconductor die and an insulating encapsulant surrounding the semiconductor die;
a first heat dissipation element located over a first surface of the insulating encapsulant, wherein the first heat dissipation element comprises a conductive base and a plurality of antenna patterns, and a ratio of a thickness of the first heat dissipation element to a thickness of the insulating encapsulant is in a range of 1:1 to 1:5, and wherein sidewalls of the first heat dissipation element are aligned with sidewalls of the insulating encapsulant; and
a plurality of conductive balls located over a second surface of the insulating encapsulant in between the insulating encapsulant and the circuit substrate.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, further comprising:
a second heat dissipation element located on the circuit substrate and electrically connected to the plurality of conductive balls.

### Claim 11 (depends on 9)

The semiconductor device according to claim 9, further comprising:
a first redistribution layer located in between the first heat dissipation element and the first surface of the insulating encapsulant, wherein the first redistribution layer comprises at least one feed line and one ground plate, and the plurality of antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer; and
a second redistribution layer located in between the plurality of conductive balls and the second surface of the insulating encapsulant.

### Claim 12 (depends on 9)

The semiconductor device according to claim 9, wherein the first heat dissipation element comprises the conductive base and a plurality of slot antenna patterns defined on the conductive base.

### Claim 13 (depends on 9)

The semiconductor device according to claim 9, wherein the first heat dissipation element comprises the conductive base and a plurality of monopole antenna patterns partially surrounded by and protruding out from the conductive base, and the plurality of monopole antenna patterns is isolated from the conductive base.

### Claim 14 (depends on 9)

The semiconductor device according to claim 9, wherein the conductive base of the first heat dissipation element comprises reflectors surrounding the plurality of antenna patterns, the plurality of antenna patterns is isolated from the reflectors, and the reflectors are electrically connected to the ground plate of the first redistribution layer.

### Claim 15 (depends on 9)

The semiconductor device according to claim 9, wherein the first heat dissipation element comprises the conductive base and a plurality of loop antenna patterns defined on the conductive base.

### Claim 16

A method of fabricating a package structure, comprising:
forming a first redistribution layer on a conductive carrier, wherein forming the first redistribution layer comprises forming at least one feed line and one ground plate, and the feed line is electrically connected to the conductive carrier;
providing a semiconductor die on the first redistribution layer and forming an insulating encapsulant surrounding the semiconductor die;
patterning the conductive carrier to form a heat dissipation element comprising a conductive base and a plurality of antenna patterns, wherein the plurality of antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer, and
performing a dicing process by cutting through the first redistribution layer, the heat dissipation element, and the insulating encapsulant so that sidewalls of the heat dissipation element are aligned with sidewalls of the insulating encapsulant.

### Claim 17 (depends on 16)

The method according to claim 16, wherein the conductive carrier is patterned by a laser drilling process or a chemical etching process.

### Claim 18 (depends on 16)

The method according to claim 16, wherein the conductive carrier is patterned to define a plurality of slot antenna patterns on the conductive base.

### Claim 19 (depends on 16)

The method according to claim 16, wherein the conductive carrier is patterned to define a plurality of loop antenna patterns on the conductive base.

### Claim 20 (depends on 16)

The method according to claim 16, wherein patterning the conductive carrier and forming the heat dissipation element further comprises patterning the conductive carrier to form the conductive base with a plurality of openings and placing a plurality of monopole antenna patterns in the plurality of openings, and the plurality of monopole antenna patterns is isolated from the conductive base.