# US 11,444,022 B2 · Semiconductor memory device

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- Number: US 11,444,022 B2
- Document ID: US11444022B2
- Status: Granted
- Kind: B2
- Application number: 17/007,230
- Filed: 2020-08-31
- Published: 2021-09-16
- Granted: 2022-09-13
- Earliest claimed: 2020-03-16
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Kaito Shirai; Hanae Ishihara
- Web page: https://patentgrep.com/patent/US11444022B2

## CPC

- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10B 43/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 90/00: Package configurations
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A semiconductor memory device includes a semiconductor substrate, a memory cell array, and first and second wirings. The semiconductor substrate includes first region to third region and fourth region to sixth region. The memory cell array includes first conducting layers extending in a second direction from the first region to the third region and laminated in a first direction, first and second semiconductor layers disposed in the first and third regions, extending in the first direction, and opposed to the first conducting layers, first and second contacts disposed in the fourth and sixth regions and extending in the first direction, and a third semiconductor layer disposed in the fifth region and extending in the first direction. The first wiring is connected to the first semiconductor layer and the second contact. The second wiring is connected to the second semiconductor layer and the third contact.

## Claims

### Claim 1

A semiconductor memory device comprising:
a semiconductor substrate;
a memory cell array disposed separately from the semiconductor substrate in a first direction intersecting with a surface of the semiconductor substrate; and
first and second wirings disposed in the first direction of the memory cell array, the first and second wirings having a distance from the semiconductor substrate larger than a distance of the memory cell array from the semiconductor substrate, wherein
the semiconductor substrate includes a first region to a third region arranged in order in a second direction intersecting with the first direction and a fourth region to a sixth region arranged in order in the second direction, wherein
in a third direction intersecting with the first direction and the second direction:
the fourth region is adjacent to the first region;
the fifth region is adjacent to the second region; and
the sixth region is adjacent to the third region; wherein
the memory cell array includes:
a plurality of first conducting layers extending in the second direction from above the first region to above the third region over the second region, the plurality of first conducting layers being laminated in the first direction together with a plurality of first insulating layers in alternation;
a plurality of second insulating layers extending in the second direction from above the fourth region to above the sixth region over the fifth region, the plurality of second insulating layers being laminated in the first direction together with the plurality of first insulating layers in alternation;
a first semiconductor layer disposed over the first region, the first semiconductor layer extending in the first direction and being opposed to the plurality of first conducting layers;
a second semiconductor layer disposed over the third region, the second semiconductor layer extending in the first direction and being opposed to the plurality of first conducting layers;
a first contact disposed over the fourth region, the first contact extending in the first direction and being opposed to the plurality of second insulating layers;
a third semiconductor layer disposed over the fifth region, the third semiconductor layer extending in the first direction and being opposed to the plurality of second insulating layers; and
a second contact disposed over the sixth region, the second contact extending in the first direction and being opposed to the plurality of second insulating layers, wherein
the first wiring extends in the third direction over the first region and the fourth region, and the first wiring is electrically connected to the first semiconductor layer and connected to the first contact, and
the second wiring extends in the third direction over the third region and the sixth region, and the second wiring is electrically connected to the second semiconductor layer and connected to the second contact.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein
the first semiconductor layer includes:
a first part extending in the first direction; and
a second part disposed between the first part and the first wiring, the second part extending in the first direction, wherein
the third semiconductor layer includes:
a third part extending in the first direction; and
a fourth part disposed in the first direction of the third part, the fourth part having a distance from the semiconductor substrate larger than a distance of the third part from the semiconductor substrate, the fourth part extending in the first direction.

### Claim 3 (depends on 2)

The semiconductor memory device according to claim 2, wherein
when a width in the second direction or the third direction of the first part of the first semiconductor layer is defined as a first width,
when a width in the second direction or the third direction of the second part of the first semiconductor layer is defined as a second width,
when a width in the second direction or the third direction of the third part of the third semiconductor layer is defined as a third width, and
when a width in the second direction or the third direction of the fourth part of the third semiconductor layer is defined as a fourth width,
the fourth width is larger than the first width, the fourth width is larger than the second width, and the fourth width is larger than the third width.

### Claim 4 (depends on 2)

The semiconductor memory device according to claim 2, wherein
when a distance between a center axis of the first part and a center axis of the second part in the second direction or the third direction of the first semiconductor layer is defined as a first distance, and
when a distance between a center axis of the third part and a center axis of the fourth part in the second direction or the third direction of the third semiconductor layer is defined as a second distance,
the second distance is larger than the first distance.

### Claim 5 (depends on 1)

The semiconductor memory device according to claim 1, wherein
when a width in the second direction or the third direction of the first semiconductor layer is defined as a fifth width, and
when a width in the second direction or the third direction of the third semiconductor layer is defined as a sixth width,
the sixth width is different from the fifth width.

### Claim 6 (depends on 1)

The semiconductor memory device according to claim 1, comprising:
a third contact that connects the first wiring to the first semiconductor layer; and
a fourth contact that connects the second wiring to the second semiconductor layer.

### Claim 7 (depends on 1)

The semiconductor memory device according to claim 1, comprising
a fifth contact disposed over the second region, the fifth contact extending in the first direction and being opposed to the plurality of second insulating layers.