# US 11,444,020 B2 · Via for semiconductor device connection and methods of forming the same

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- Number: US 11,444,020 B2
- Document ID: US11444020B2
- Status: Granted
- Kind: B2
- Application number: 16/846,750
- Filed: 2020-04-13
- Published: 2020-07-30
- Granted: 2022-09-13
- Earliest claimed: 2018-02-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chen-Hua Yu; An-Jhih Su; Chi-Hsi Wu; Wen-Chih Chiou; Tsang-Jiuh Wu; Der-Chyang Yeh; Ming Shih Yeh
- Web page: https://patentgrep.com/patent/US11444020B2

## CPC

- H10H 20/01: Manufacture or treatment
- H10W 20/42: Vias, e.g. via plugs
- H10H 20/018: {Bonding of wafers}
- H10H 20/831: characterised by their shape
- H10H 20/857: Interconnections, e.g. lead-frames, bond wires or solder balls
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 50/283: {by chemical means}
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 95/062: {involving a dielectric removal step}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/092: {by smoothing the dielectric parts}
- H10W 20/098: {by filling between adjacent conductive parts}
- H10W 20/43: Layouts of interconnections
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/90: Bond pads, in general
- H10W 74/016: {using moulds}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/00: Package configurations
- H10H 20/01335: {the light-emitting regions comprising nitride materials}
- H10H 20/032: {of electrodes}
- H10H 20/034: {of coatings}
- H10H 20/0362: {of encapsulations}
- H10H 20/0364: {of interconnections}
- H10H 20/812: within the light-emitting regions, e.g. having quantum confinement structures
- H10H 20/825: containing nitrogen, e.g. GaN
- H10P 52/403: {of conductive or resistive materials}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7432: {used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/01904: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/853: {On the same surface}
- H10W 72/874: {On different surfaces}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/01: Manufacture or treatment
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/314: {characterized by direct bonding of pads or other interconnections}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/754: {having material changed during the connecting}
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/722: {between stacked chips}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

## Claims

### Claim 1

A device comprising:
a first metal pad and a second metal pad on a substrate;
a component device over the first metal pad, the component device comprising a bottom terminal, a top terminal, and one or more semiconductor layers, the bottom terminal and the top terminal being disposed on opposite sides of the one or more semiconductor layers, the bottom terminal electrically coupling the one or more semiconductor layers to the first metal pad, wherein the bottom terminal and the top terminal are in contact with the one or more semiconductor layers;
a gap fill material surrounding the component device;
a conductive via over the second metal pad, the conductive via extending through the gap fill material to the second metal pad, wherein a top surface of the gap fill material is level with a top surface of the conductive via; and
an interconnect electrically coupling the top terminal of the component device to the conductive via.

### Claim 2 (depends on 1)

The device of claim 1, wherein the component device is a diode, and wherein at least a portion of a top surface of the one or more semiconductor layers is exposed through the top terminal.

### Claim 3 (depends on 1)

The device of claim 1, wherein the component device has a width of between about 10 μm and about 50 μm.

### Claim 4 (depends on 1)

The device of claim 1, wherein a bottom surface of the conductive via is disposed below a bottom surface of the bottom terminal.

### Claim 5 (depends on 1)

The device of claim 1, wherein the bottom terminal is bonded to the first metal pad by a metal-to-metal bond.

### Claim 6 (depends on 1)

The device of claim 1, wherein a top surface of the conductive via is disposed above a top surface of the top terminal.

### Claim 7 (depends on 1)

The device of claim 1, wherein the one or more semiconductor layers comprise alternating layers of a p-type doped semiconductor material and an n-type doped semiconductor material.

### Claim 8 (depends on 1)

The device of claim 1, wherein the one or more semiconductor layers comprise a layer of indium gallium nitride (InGaN) and a layer of gallium nitride (GaN).

### Claim 9

A semiconductor device comprising:
a first metal pad and a second metal pad over a first substrate;
a component device over the first substrate, the component device comprising a bottom terminal bonded to the first metal pad, the component device further comprising a top terminal;
a protective layer in contact with sidewalls of the bottom terminal and the top terminal;
a gap fill material over and surrounding the protective layer;
a conductive via extending through the gap fill material and the protective layer, the conductive via being connected to the second metal pad; and
a redistribution line extending through the gap fill material and the protective layer, the redistribution line connecting the top terminal to the conductive via.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further comprising a passivation layer extending along surfaces of the gap fill material, the redistribution line, and the component device.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the component device comprises an n-type doped semiconductor layer, a p-type doped semiconductor layer, and a multiple quantum well.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the multiple quantum well comprises alternating layers of indium gallium nitride (InGaN) and gallium nitride (GaN).

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the bottom terminal is solder bonded to the first metal pad.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein the top terminal is ring-shaped in a top-down view.

### Claim 15

A semiconductor device comprising:
a first substrate comprising a first terminal and a second terminal;
a first component device comprising a third terminal bonded to the first terminal;
a gap fill material over the first substrate and the first component device, the gap fill material surrounding the first component device;
a conductive via extending from a top surface of the gap fill material to the second terminal; and
a fourth terminal over a top surface of the first component device, the fourth terminal connecting the first component device to the second terminal through the conductive via, wherein the fourth terminal is in contact with a first semiconductor material of the first component device.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the fourth terminal extends at least partially through the gap fill material.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, further comprising a redistribution line connecting the fourth terminal to the conductive via.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the fourth terminal comprises a ring-shape in a top-down view.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, further comprising an optically transparent passivation layer over the gap fill material and the fourth terminal.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein a height of the conductive via is greater than a combined height of the first component device and the fourth terminal.