# US 11,444,019 B2 · Package comprising a substrate with interconnect routing over solder resist layer and an integrated device coupled to the substrate and method for manufacturing the package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,019 B2 - Document ID: US11444019B2 - Status: Granted - Kind: B2 - Application number: 16/840,752 - Filed: 2020-04-06 - Published: 2021-10-07 - Granted: 2022-09-13 - Earliest claimed: 2020-04-06 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Aniket Patil; Hong Bok We; Kuiwon Kang - Web page: https://patentgrep.com/patent/US11444019B2 ## CPC - H10W 20/42: Vias, e.g. via plugs - H10W 70/611: {for connecting multiple chips together} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 70/69: Insulating materials thereof - H10W 72/30: Die-attach connectors - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/131: {the semiconductor body being only partially enclosed} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/00: Package configurations - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/635: {Through-vias} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/731: {of die-attach connectors} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes (i) at least one inner dielectric layer, (ii) a plurality of interconnects located in the at least one inner dielectric layer, where the plurality of interconnects includes a pad located on a bottom metal layer of the substrate, (iii) an outer dielectric layer located over the at least one dielectric layer, (iv) at least one routing interconnect coupled to the plurality of interconnects, where the at least one routing interconnect is located over the outer dielectric layer, where the at least one routing interconnect is located below the bottom metal layer of the substrate, and (v) a cover dielectric layer located over the outer dielectric layer and the at least one routing interconnect. The package includes a solder interconnect coupled to the pad located on the bottom metal layer of the substrate. ## Claims ### Claim 1 A package comprising: a substrate comprising: (i) at least one inner dielectric layer; (ii) a plurality of interconnects located in the at least one inner dielectric layer, wherein the plurality of interconnects includes a pad located on a bottom metal layer of the substrate; (iii) an outer dielectric layer located over the at least one inner dielectric layer; (iv) at least one routing interconnect coupled to the plurality of interconnects, wherein the at least one routing interconnect is located over the outer dielectric layer, wherein the at least one routing interconnect is located over the bottom metal layer of the substrate, and (v) a cover dielectric layer located over the outer dielectric layer and the at least one routing interconnect; an integrated device coupled to the substrate; and a solder interconnect coupled to the pad located on the bottom metal layer of the substrate. ### Claim 2 (depends on 1) The package of claim 1, wherein the outer dielectric layer includes a different material than the at least one inner dielectric layer. ### Claim 3 (depends on 1) The package of claim 1, wherein the cover dielectric layer includes a different material than the at least one inner dielectric layer. ### Claim 4 (depends on 1) The package of claim 1, wherein the cover dielectric layer includes a different material than the at least one inner dielectric layer and the outer dielectric layer. ### Claim 5 (depends on 1) The package of claim 1, wherein the cover dielectric layer and the outer dielectric layer each includes a different material than the at least one inner dielectric layer. ### Claim 6 (depends on 1) The package of claim 1, wherein the cover dielectric layer and the outer dielectric layer each includes a same material. ### Claim 7 (depends on 1) The package of claim 1, wherein the at least one inner dielectric layer includes a copper clad laminate (CCL) core, a prepreg, an ajinomoto build up film (ABF), and/or a resin coated copper (RCC). ### Claim 8 (depends on 1) The package of claim 1, wherein the outer dielectric layer and the cover dielectric layer, each includes a solder resist layer and/or a photo imagable dielectric (PID). ### Claim 9 (depends on 1) The package of claim 1, wherein a first electrical signal to and/or from the integrated device is configured to travel through the at least one routing interconnect. ### Claim 10 (depends on 1) The package of claim 1, further comprising: an encapsulation layer located over the substrate; at least one via located in the encapsulation layer; at least one upper routing interconnect coupled to the at least one via, wherein the at least one upper routing interconnect is located over the encapsulation layer; an upper cover dielectric layer located over the at least one upper routing interconnect and the encapsulation layer, wherein the outer dielectric layer is located below a bottom surface of the at least one inner dielectric layer, wherein the at least one routing interconnect is located below bottom surface of the outer dielectric layer, and wherein the cover dielectric layer is located below the bottom surface of the outer dielectric layer and the at least one routing interconnect. ### Claim 11 (depends on 10) The package of claim 10, wherein a first electrical signal to and/or from the integrated device is configured to travel through the at least one upper routing interconnect. ### Claim 12 (depends on 10) The package of claim 10, wherein the package is part of a package on package (PoP). ### Claim 13 (depends on 1) The package of claim 1, wherein the bottom metal layer of the substrate is a metal layer that is vertically closest to the solder interconnect without being laterally positioned next to the solder interconnect. ### Claim 14 (depends on 1) The package of claim 1, wherein the package is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle. ### Claim 15 An apparatus comprising: a substrate comprising: (i) at least one inner dielectric layer; (ii) a plurality of interconnects located in the at least one inner dielectric layer, wherein the plurality of interconnects includes a pad located on a bottom metal layer of the substrate; (iii) an outer dielectric layer located over the at least one inner dielectric layer; (iv) means for routing interconnect coupled to the plurality of interconnects, wherein the means for routing interconnect is located over the outer dielectric layer, wherein the means for routing interconnect is located over the bottom metal layer of the substrate, and (v) a cover dielectric layer located over the outer dielectric layer and the means for routing interconnect; an integrated device coupled to the substrate; and a solder interconnect coupled to the pad located on the bottom metal layer of the substrate. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the outer dielectric layer includes a different material than the at least one inner dielectric layer. ### Claim 17 (depends on 15) The apparatus of claim 15, wherein the cover dielectric layer includes a different material than the at least one inner dielectric layer. ### Claim 18 (depends on 15) The apparatus of claim 15, wherein the cover dielectric layer includes a different material than the at least one inner dielectric layer and the outer dielectric layer. ### Claim 19 (depends on 15) The apparatus of claim 15, wherein the cover dielectric layer and the outer dielectric layer each includes a different material than the at least one inner dielectric layer. ### Claim 20 (depends on 15) The apparatus of claim 15, wherein the cover dielectric layer and the outer dielectric layer each includes a same material. ### Claim 21 (depends on 15) The apparatus of claim 15, wherein a first electrical signal to and/or from the integrated device is configured to travel through the means for routing interconnect. ### Claim 22 (depends on 15) The apparatus of claim 15, further comprising: means for encapsulation located over the substrate; at least one via located in the means for encapsulation; means for upper routing interconnect coupled to the at least one via, wherein the means for upper routing interconnect is located over the means for encapsulation; and an upper cover dielectric layer located over the means for upper routing interconnect and the means for encapsulation. ### Claim 23 (depends on 22) The apparatus of claim 22, wherein a first electrical signal to and/or from the integrated device is configured to travel through the means for upper routing interconnect. ### Claim 24 (depends on 15) The apparatus of claim 15, wherein the outer dielectric layer is (i) coupled to the at least one inner dielectric layer and (ii) located below the at least one inner dielectric layer, wherein the means for routing interconnect is located below the outer dielectric layer, and wherein the cover dielectric layer is (i) coupled to the outer dielectric layer and the means for routing interconnect, and (ii) located below the outer dielectric layer. ### Claim 25 A package comprising: a substrate comprising: (i) at least one inner dielectric layer; (ii) a plurality of interconnects located in the at least one inner dielectric layer, wherein the plurality of interconnects includes a pad located on a bottom metal layer of the substrate; (iii) a first outer dielectric layer located over the at least one inner dielectric layer; (iv) a cover dielectric layer located over the at least one inner dielectric layer; (v) at least one routing interconnect coupled to the plurality of interconnects, wherein the at least one routing interconnect is located over the cover dielectric layer, wherein the at least one routing interconnect is located over the bottom metal layer of the substrate, and (vi) a second outer dielectric layer located over the cover dielectric layer and the at least one routing interconnect; an integrated device coupled to the substrate; and a solder interconnect coupled to the pad located on the bottom metal layer of the substrate. ### Claim 26 (depends on 25) The package of claim 25, wherein the second outer dielectric layer and the first outer dielectric layer are a same dielectric layer. ### Claim 27 A method for fabricating package, comprising: providing a substrate comprising: (i) at least one inner dielectric layer; (ii) a plurality of interconnects located in the at least one inner dielectric layer, wherein the plurality of interconnects includes a pad located on a bottom metal layer of the substrate; (iii) an outer dielectric layer located over the at least one inner dielectric layer; (iv) at least one routing interconnect coupled to the plurality of interconnects, wherein the at least one routing interconnect is located over the outer dielectric layer, wherein the at least one routing interconnect is located over the bottom metal layer of the substrate, and (v) a cover dielectric layer located over the outer dielectric layer and the at least one routing interconnect; coupling an integrated device to the substrate; and coupling a solder interconnect to the pad located on the bottom metal layer of the substrate. ### Claim 28 (depends on 27) The method of claim 27, further comprising: forming an encapsulation layer over the substrate; forming at least one via in the encapsulation layer; forming at least one upper routing interconnect over the encapsulation layer, wherein the at least one upper routing interconnect is coupled to the at least one via; and forming an upper cover dielectric layer over the at least one upper routing interconnect and the encapsulation layer.