# US 11,444,017 B2 · Semiconductor package and method of manufacturing a semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,017 B2 - Document ID: US11444017B2 - Status: Granted - Kind: B2 - Application number: 16/560,139 - Filed: 2019-09-04 - Published: 2020-03-05 - Granted: 2022-09-13 - Earliest claimed: 2018-09-05 - Assignees: Infineon Technologies Austria AG - Applicants: Infineon Technologies Austria AG - Inventors: Sergey Yuferev; Robert Fehler; Petteri Palm - Web page: https://patentgrep.com/patent/US11444017B2 ## CPC - H10W 20/42: Vias, e.g. via plugs - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - G06F 30/394: Routing (G06F30/396 takes precedence) - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 20/081: {by forming openings in the dielectric parts} - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 72/019: {of bond pads} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/0198: {batch processes} - H10W 72/9413: {on encapsulations} - H10W 72/944: {Dispositions of multiple bond pads} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In an embodiment, a semiconductor package includes a semiconductor device embedded in an insulating layer, a contact pad having an area, and a vertical redistribution structure including substantially parallel vertical paths arranged in the insulating layer and extending perpendicular to the area of the contact pad. The substantially vertical paths are non-uniformly distributed over the area of the contact pad. ## Claims ### Claim 1 A semiconductor package, comprising: a semiconductor device embedded in an insulating layer; a contact pad having an area that does not overlap the semiconductor device, and a vertical current redistribution structure comprising substantially parallel vertical current paths arranged in the insulating layer and extending perpendicular to the area of the contact pad that does not overlap the semiconductor device, the substantially parallel vertical current paths being non-uniformly distributed over the area of the contact pad that does not overlap the semiconductor device. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the substantially parallel vertical current paths are arranged in a L-shape, U shape or O-shape on the contact pad. ### Claim 3 (depends on 1) The semiconductor package of claim 1, further comprising a plurality of via sites forming a two-dimensional array of a first pitch on the area of the contact pad that does not overlap the semiconductor device, wherein the substantially parallel vertical current paths comprise conductive vias extending through the insulating layer and located at a subset of the via sites such that the two-dimensional array includes at least one via-free zone in the two-dimensional array. ### Claim 4 (depends on 3) The semiconductor package of claim 3, wherein the at least one via-free zone has a lateral shape such that the conductive vias are arranged in a L-shape, U shape, O-shape on the area. ### Claim 5 (depends on 3) The semiconductor package of claim 3, wherein the via sites are arranged in off-set rows or in rows and columns. ### Claim 6 (depends on 3) The semiconductor package of claim 3, wherein a first contact pad is arranged on a first major surface of the insulating layer and the conductive vias extend between the first contact pad and a lateral conductive layer positioned on a second major surface of the insulating layer, the second major surface opposing the first major surface. ### Claim 7 (depends on 6) The semiconductor package of claim 6, wherein the conductive vias are positioned adjacent and spaced apart from a side face of the semiconductor device and the at least one via-free zone is located adjacent an outer edge of the insulating layer. ### Claim 8 (depends on 6) The semiconductor package of claim 6, wherein the first contact pad is arranged on the insulating layer and the conductive vias extend between the first contact pad and a first device contact pad arranged on a first major surface of the semiconductor device. ### Claim 9 (depends on 6) The semiconductor package of claim 6, wherein the first contact pad is arranged on the semiconductor device and the conductive vias extend between the first contact pad and the lateral conductive layer positioned on the second major surface of the insulating layer. ### Claim 10 (depends on 3) The semiconductor package of claim 3, further comprising: a device contact pad on a major surface of the semiconductor device, the device contact pad having a second area, a set of second via sites forming a two-dimensional array of a second pitch on the second area; and conductive vias extending through the insulating layer and located at a subset of the second via sites and such that the two-dimensional array includes at least one via-free zone in the two-dimensional array, the conductive vias extending between the device contact pad and a lateral conductive layer.