# US 11,444,016 B2 · Non-volatile memory with capacitors using metal under signal line or above a device capacitor

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- Number: US 11,444,016 B2
- Document ID: US11444016B2
- Status: Granted
- Kind: B2
- Application number: 16/886,695
- Filed: 2020-05-28
- Published: 2020-09-17
- Granted: 2022-09-13
- Earliest claimed: 2018-07-05
- Assignees: SanDisk Technologes LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Luisa Lin; Mohan Dunga; Venkatesh P. Ramachandra; Peter Rabkin; Masaaki Higashitani
- Web page: https://patentgrep.com/patent/US11444016B2

## CPC

- H10D 1/714: {having horizontal extensions}
- H10W 20/496: {Capacitor integral with wiring layers}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 1/692: {Electrodes}
- H10D 84/813: {Combinations of field-effect devices and capacitor only}
- H10W 20/427: {Power or ground buses}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 72/90: Bond pads, in general
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.

## Claims

### Claim 1

An apparatus, comprising:
a semiconductor die, comprising:
a substrate;
a three dimensional non-volatile memory array formed above the substrate;
a plurality of metal interconnect layers configured to route signals within the semiconductor die, the plurality of metal interconnect layers are positioned above the substrate, above the three dimensional non-volatile memory array and across a top area of the semiconductor die;
electrical components, including a device capacitor, positioned in the semiconductor die on a top surface of the substrate and below the plurality of metal interconnect layers, the metal interconnect layers are electrically connected to the electrical components below the plurality of metal interconnect layers;
an I/O pad; and
multiple capacitors connected to the I/O pad, the multiple capacitors are positioned in the metal interconnect layers, at least one of the multiple capacitors is positioned directly above the device capacitor in the semiconductor die.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising:
a signal line connected to the electrical components, the multiple capacitors are positioned directly below the signal line.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein:
the I/O pad is a power I/O pad.

### Claim 4 (depends on 3)

The apparatus of claim 3, further comprising:
a ground I/O pad, the multiple capacitors are also connected to the ground I/O pad.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein:
at least one of the multiple capacitors comprises two metal components in a single metal interconnect layer of the plurality of metal interconnect layers.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein:
the two metal components are shaped as interleaved combs.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein:
the two metal components have interdigitated fingers.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein:
the metal interconnect layers include a first metal interconnect layer and a second metal interconnect layer below the first metal interconnect layer; and
at least one of the multiple capacitors comprises a pair of metal components that includes a first metal component in the first metal interconnect layer and a second metal component in the second metal interconnect layer.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein:
the first metal component is a mesh.

### Claim 10 (depends on 8)

The apparatus of claim 8, wherein:
the first metal component is a metal plate.

### Claim 11 (depends on 8)

The apparatus of claim 8, wherein:
the first metal component is comb shaped.

### Claim 12 (depends on 4)

The apparatus of claim 4, wherein:
the multiple capacitors comprise a first capacitor, a second capacitor, a third capacitor and a fourth capacitor;
the plurality of metal interconnect layers includes a first metal interconnect layer having a first metal interconnect layer region and a second metal interconnect layer having a second metal interconnect layer region;
the first metal interconnect layer region includes a first metal component connected to the ground I/O pad and a second metal component connected to the power I/O pad;
the second metal interconnect layer region includes a third metal component connected to the power I/O pad and a fourth metal component ground I/O pad;
the first capacitor comprises the first metal component and the second metal component;
the second capacitor comprises the third metal component and the fourth metal component;
the third capacitor comprises the first metal component and the third metal component; and
the fourth capacitor comprises the second metal component and the fourth metal component.