# US 11,444,014 B2 · Semiconductor packages including an insulating layer including a recessed surface and methods of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,014 B2 - Document ID: US11444014B2 - Status: Granted - Kind: B2 - Application number: 16/830,361 - Filed: 2020-03-26 - Published: 2021-03-25 - Granted: 2022-09-13 - Earliest claimed: 2019-09-19 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jinho Chun; Jin Ho An; Teahwa Jeong; Jeonggi Jin; Ju-Il Choi; Atsushi Fujisaki - Web page: https://patentgrep.com/patent/US11444014B2 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/685: comprising multiple insulating layers - H10W 74/114: {by a substrate and the encapsulations} - H10W 70/69: Insulating materials thereof - H10W 70/695: Organic materials - H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract There are provided semiconductor packages including a redistribution substrate and a semiconductor chip mounted on the redistribution substrate. The redistribution substrate may include a lower protective layer, a first conductive pattern disposed on the lower protective layer, a first insulating layer surrounding the first conductive pattern and disposed on the lower protective layer, and a second insulating layer disposed on the first insulating layer. The first insulating layer may include a first upper surface that includes a first flat portion extending parallel to an upper surface of the lower protective layer, and a first recess facing the lower protective layer and in contact with the first conductive pattern. The first recess may be directly connected to the first conductive pattern. ## Claims ### Claim 1 A semiconductor package comprising: a redistribution substrate; and a semiconductor chip on the redistribution substrate, wherein the redistribution substrate includes: a lower protective layer; a first conductive pattern on the lower protective layer; a first insulating layer surrounding the first conductive pattern and on the lower protective layer, the first insulating layer including a first upper surface that includes a first flat portion extending parallel to an upper surface of the lower protective layer and a first recess, and the first insulating layer contacting a side surface of the first conductive pattern, wherein the side surface of the first conductive pattern extends between an upper surface and a lower surface of the first conductive pattern; and a second insulating layer on the first insulating layer, wherein the first recess is closer than the first flat portion to the upper surface of the first conductive pattern, the first recess is recessed toward the lower protective layer with respect to both the upper surface of the first conductive pattern and the first flat portion of the first upper surface of the first insulating layer, and the first flat portion of the first upper surface of the first insulating layer is coplanar with the upper surface of the first conductive pattern. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the second insulating layer is in contact with the first upper surface of the first insulating layer, and a portion of the second insulating layer is in the first recess of the first insulating layer. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein the first recess includes a side surface that is directly connected to the first conductive pattern and is inclined with respect to the upper surface of the lower protective layer, a distance between a first portion of the side surface of the first recess and the side surface of the first conductive pattern is longer than a distance between a second portion of the side surface of the first recess and the side surface of the first conductive pattern, and a distance from the upper surface of the lower protective layer to the first portion of the side surface of the first recess is shorter than a distance from the upper surface of the lower protective layer to the second portion of the side surface. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein the first recess includes a side surface and a lower surface, and the side surface of the first recess is directly connected to the first conductive pattern and is between the first conductive pattern and the lower surface of the first recess, and a distance from the upper surface of the lower protective layer to the lower surface of the first recess is 0.7 to 0.9 times a distance from the upper surface of the lower protective layer to the first flat portion of the first upper surface of the first insulating layer. ### Claim 5 (depends on 1) The semiconductor package of claim 1, further comprising a second conductive pattern on the first conductive pattern, wherein the second insulating layer includes a second upper surface that includes a second flat portion extending parallel to the upper surface of the lower protective layer, and the second upper surface of the second insulating layer further includes a second recess that is between the second flat portion of the second upper surface of the second insulating layer and the second conductive pattern. ### Claim 6 (depends on 1) The semiconductor package of claim 1, further comprising: a second conductive pattern on the first conductive pattern; and a terminal pad that is on the second insulating layer and electrically connects the second conductive pattern to the semiconductor chip. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein the first recess of the first upper surface of the first insulating layer surrounds the first conductive pattern in a plan view. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the lower surface of the first conductive pattern and a lower surface of the first insulating layer are coplanar with each other. ### Claim 9 A semiconductor package comprising: a lower protective layer; a first conductive pattern on the lower protective layer; a first insulating layer on the lower protective layer and contacting a side surface of the first conductive pattern, wherein the side surface of the first conductive pattern extends between an upper surface and a lower surface of the first conductive pattern; a second insulating layer on the first insulating layer and the first conductive pattern; and a semiconductor chip on the second insulating layer, wherein the first insulating layer includes a first upper surface and an inclined surface adjacent to the side surface of the first conductive pattern, the first upper surface of the first insulating layer extends parallel to an upper surface of the lower protective layer, a distance from the upper surface of the lower protective layer to the first upper surface of the first insulating layer is equal to a distance from the upper surface of the lower protective layer to the upper surface of the first conductive pattern, and a distance from the upper surface of the lower protective layer to a first portion of the inclined surface of the first insulating layer is different from a distance from the upper surface of the lower protective layer to a second portion of the inclined surface of the first insulating layer, wherein the inclined surface of the first insulating layer is between the first conductive pattern and the first upper surface of the first insulating layer. ### Claim 10 (depends on 9) The semiconductor package of claim 9, wherein a distance between the first portion of the inclined surface and the side surface of the first conductive pattern is longer than a distance between the second portion of the inclined surface and the side surface of the first conductive pattern, and the distance from the upper surface of the lower protective layer to the first portion of the inclined surface is shorter than the distance from the upper surface of the lower protective layer to the second portion of the inclined surface. ### Claim 11 (depends on 9) The semiconductor package of claim 9, wherein a distance between the first portion of the inclined surface and the side surface of the first conductive pattern is longer than a distance between the second portion of the inclined surface and the side surface of the first conductive pattern, and the distance from the upper surface of the lower protective layer to the first portion of the inclined surface is longer than the distance from the upper surface of the lower protective layer to the second portion of the inclined surface. ### Claim 12 (depends on 9) The semiconductor package of claim 9, further comprising: a second conductive pattern extending through the second insulating layer and contacting the first conductive pattern, wherein the second conductive pattern is electrically connected with the semiconductor chip; and an upper protective layer on the second insulating layer and the second conductive pattern. ### Claim 13 (depends on 9) The semiconductor package of claim 9, wherein the first conductive pattern is between the semiconductor chip and the lower protective layer. ### Claim 14 A semiconductor package comprising: a redistribution substrate; a semiconductor chip on the redistribution substrate; and a molding film on the redistribution substrate and on a side surface of the semiconductor chip, wherein the redistribution substrate includes: a lower protective layer; a first conductive pattern on the lower protective layer; a first insulating layer on the lower protective layer and surrounding the first conductive pattern; a second insulating layer on the first insulating layer and the first conductive pattern; and a terminal pad on the second insulating layer and electrically connected to the semiconductor chip, and wherein the first insulating layer includes an inclined surface, a first upper surface and a second upper surface, the first upper surface is between the inclined surface and the second upper surface and extends parallel to an upper surface of the lower protective layer, the second upper surface is coplanar with an upper surface of the first conductive pattern, the lower protective layer, the first insulating layer, and the second insulating layer are stacked in a first direction, a distance from the upper surface of the lower protective layer to the first upper surface in the first direction is shorter than a distance from the upper surface of the lower protective layer to the second upper surface in the first direction, and a distance from the upper surface of the lower protective layer to a first portion of the inclined surface in the first direction is different from a distance from the upper surface of the lower protective layer to a second portion of the inclined surface in the first direction. ### Claim 15 (depends on 14) The semiconductor package of claim 14, wherein a distance between the first portion of the inclined surface and a side surface of the first conductive pattern in a second direction is longer than a distance between the second portion of the inclined surface and the side surface of the first conductive pattern in the second direction, and the second direction is perpendicular to the first direction, and the distance from the upper surface of the lower protective layer to the first portion of the inclined surface in the first direction is shorter than the distance from the upper surface of the lower protective layer to the second portion of the inclined surface in the first direction. ### Claim 16 (depends on 14) The semiconductor package of claim 14, wherein a distance between the first portion of the inclined surface and a side surface of the first conductive pattern in the first direction is longer than a distance between the second portion of the inclined surface and the side surface of the first conductive pattern in the first direction, and the distance from the upper surface of the lower protective layer to the first portion of the inclined surface in the first direction is greater than the distance from the upper surface of the lower protective layer to the second portion of the inclined surface in the first direction. ### Claim 17 (depends on 14) The semiconductor package of claim 14, further comprising: a second conductive pattern extending from the upper surface of the first conductive pattern onto the first insulating layer and extending between the second insulating layer and the first insulating layer; and a third conductive pattern extending through the second insulating layer and electrically connected to the second conductive pattern. ### Claim 18 (depends on 14) The semiconductor package of claim 14, wherein the first insulating layer and the second insulating layer include a photosensitive insulating material.