# US 11,444,011 B2 · Semiconductor package with leadframe interconnection structure

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,444,011 B2
- Document ID: US11444011B2
- Status: Granted
- Kind: B2
- Application number: 17/095,947
- Filed: 2020-11-12
- Published: 2021-03-04
- Granted: 2022-09-13
- Earliest claimed: 2018-10-25
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Woon Yik Yong; Andreas Kucher; Chia-Yen Lee; Shao Ping Wan
- Web page: https://patentgrep.com/patent/US11444011B2

## CPC

- H10W 70/415: {Leadframe inner leads serving as die pads}
- H10W 90/811: {Multiple chips on leadframes}
- H01S 5/0231: Stems
- H01S 5/0232: Lead-frames
- H01S 5/02325: Mechanically integrated components on mount members or optical micro-benches
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- G01S 7/4814: {of transmitters alone}
- G01S 7/4815: {using multiple transmitters}
- H01S 5/02216: Butterfly-type, i.e. with electrode pins extending horizontally from the housings
- H01S 5/02234: Resin-filled housings; the housings being made of resin
- H01S 5/042: Electrical excitation {; Circuits therefor (monolithically integrated laser drive components H01S5/0261)}
- H01S 5/4025: {Array arrangements, e.g. constituted by discrete laser diodes or laser bar (H01S5/42 takes precedence)}
- H10W 70/427: {Bent parts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H01S: DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- G01S: RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES

## Abstract

An embodiment of a semiconductor package includes a leadframe having leads, a mold compound partly encasing the leadframe so that the leads protrude from the mold compound, a power transistor die attached to the leadframe at a first side of the leadframe, and a driver die attached to the leadframe at a second side of the leadframe opposite the first side so that the power transistor die and the driver die are disposed in a stacked arrangement. The driver die is configured to control the power transistor die. The driver die is in direct electrical communication with the power transistor die only through the leadframe and any interconnects which attach the power transistor die and the driver die to the leadframe. Corresponding methods of manufacturing the semiconductor package are also described.

## Claims

### Claim 1

A semiconductor package, comprising:
a leadframe comprising leads;
a mold compound partly encasing the leadframe so that the leads protrude from the mold compound;
a power transistor die attached to the leadframe at a first side of the leadframe; and
a driver die attached to the leadframe at a second side of the leadframe opposite the first side so that the power transistor die and the driver die are disposed in a stacked arrangement, the driver die configured to control the power transistor die,
wherein the driver die is in direct electrical communication with the power transistor die only through the leadframe and any interconnects which attach the power transistor die and the driver die to the leadframe.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, further comprising:
a first metal clip attached to a side of the power transistor die facing away from the first side of the leadframe; and
a second metal clip attached to a side of the driver transistor die facing away from the second side of the leadframe,
wherein a surface of the first metal clip facing away from the first side of the leadframe is not covered by the mold compound and a surface of the second metal clip facing away from the second side of the leadframe is not covered by the mold compound, so that the semiconductor package has double-sided cooling via the first and the second metal clips.

### Claim 3 (depends on 2)

The semiconductor package of claim 2, wherein the first metal clip is a Cu clip, and wherein the second metal clip is a Cu clip.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein the power transistor die includes a semiconductor device configured as a switch or a rectifier.

### Claim 5 (depends on 4)

The semiconductor package of claim 4, wherein the driver die is configured to switch on and off the semiconductor device included in the power transistor die.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein the power transistor die is a power MOSFET (metal-oxide semiconductor field-effect transistor) die, an IGBT (insulated gate bipolar transistor) die, a JFET (junction FET) die, or a HEMT (high-electron mobility transistor) die.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, wherein the interconnects comprise solder bumps and/or Cu pillars which attach the power transistor die and the driver die to the leadframe.

### Claim 8

A method of manufacturing a plurality of semiconductor packages, the method comprising:
singulating a first semiconductor wafer which includes a plurality of power transistor dies into separate transistor dies;
singulating a second semiconductor wafer which includes a plurality of power semiconductor driver dies into separate driver dies;
providing a plurality of leadframes, each leadframe having leads configured to receive a semiconductor die;
attaching the transistor dies to the leads of the leadframes at a bottom side of the leadframes in a flip-chip configuration;
attaching a first metal clip to a side of each transistor die facing away from the corresponding leadframe;
flipping the leadframes so that a top side of the leadframes face upward;
attaching the driver dies to the leads of the leadframes at the top side of the leadframes in a flip-chip configuration;
attaching a second metal clip to a side of each driver die facing away from the corresponding leadframe; and
partly encasing the leadframes in a mold compound.

### Claim 9 (depends on 8)

The method of claim 8, wherein the transistor dies are attached to the leads of the leadframes at the bottom side of the leadframes by solder bumps or Cu pillars.

### Claim 10 (depends on 8)

The method of claim 8, wherein the driver dies are attached to the leads of the leadframes at the top side of the leadframes by solder bumps or Cu pillars.

### Claim 11 (depends on 8)

The method of claim 8, wherein the first metal clips are Cu clips, and wherein the second metal clips are Cu clips.

### Claim 12 (depends on 8)

The method of claim 8, wherein the leadframes are partly encased in the mold compound using a FAM (film-assist molding) process.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
using inserts during the FAM process such that a surface of each first metal clip facing away from the corresponding leadframe is not covered by the mold compound, and such that a surface of each second metal clip facing away from the corresponding leadframe also is not covered by the mold compound.

### Claim 14

A method of manufacturing a semiconductor package, the method comprising:
providing a leadframe comprising leads;
partly encasing the leadframe in a mold compound so that the leads protrude from the mold compound;
attaching a power transistor die to the leadframe at a first side of the leadframe; and
attaching a driver die to the leadframe at a second side of the leadframe opposite the first side so that the power transistor die and the driver die are disposed in a stacked arrangement, the driver die configured to control the power transistor die,
wherein the driver die is in direct electrical communication with the power transistor die only through the leadframe and any interconnects which attach the power transistor die and the driver die to the leadframe.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
before partly encasing the leadframe in the mold compound, attaching a first metal clip to a side of the power transistor die facing away from the first side of the leadframe and attaching a second metal clip to a side of the driver transistor die facing away from the second side of the leadframe,
wherein a surface of the first metal clip facing away from the first side of the leadframe is not covered by the mold compound and a surface of the second metal clip facing away from the second side of the leadframe is not covered by the mold compound, so that the semiconductor package has double-sided cooling via the first and the second metal clips.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first metal clip is a Cu clip, and wherein the second metal clip is a Cu clip.

### Claim 17 (depends on 14)

The method of claim 14, wherein the driver die and the power transistor die are each attached to the leadframe in a flip-chip configuration.

### Claim 18 (depends on 14)

The method of claim 14, wherein the power transistor die includes a semiconductor device configured as a switch or a rectifier.

### Claim 19 (depends on 18)

The method of claim 18, wherein the driver die is configured to switch on and off the semiconductor device included in the power transistor die.

### Claim 20 (depends on 14)

The method of claim 14, wherein the power transistor die is a power MOSFET (metal-oxide semiconductor field-effect transistor) die, an IGBT (insulated gate bipolar transistor) die, a JFET (junction FET) die, or a HEMT (high-electron mobility transistor) die.