# US 11,444,009 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,009 B2 - Document ID: US11444009B2 - Status: Granted - Kind: B2 - Application number: 16/868,886 - Filed: 2020-05-07 - Published: 2020-11-19 - Granted: 2022-09-13 - Earliest claimed: 2019-05-16 - Assignees: Rohm Co., Ltd. - Applicants: Rohm Co., Ltd. - Inventors: Hirotaka Otake - Web page: https://patentgrep.com/patent/US11444009B2 ## CPC - H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00} - H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT] - H10D 84/0123: {Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs} - H10D 84/05: using Group III-V technology - H10D 84/82: of only field-effect components - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 70/466: {Tape carriers or flat leads} - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 90/811: {Multiple chips on leadframes} - H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs} - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10D 64/111: {Field plates} - H10D 64/602: {Heterojunction gate electrodes for FETs} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/536: {the connected ends being ball-shaped} - H10W 72/5363: {the connected ends being wedge-shaped} - H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/127: {characterised by arrangements for sealing or adhesion} - H10W 90/753: {between laterally-adjacent chips} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes: a first transistor provided with an electron transit layer made of a nitride semiconductor, a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor that includes a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode and the second drain electrode are electrically connected to each other, while the first source electrode and the second source electrode are not electrically connected to each other. ## Claims ### Claim 1 A semiconductor device comprising: a first transistor that includes an electron transit layer made of a nitride semiconductor, a first gate electrode, a first source electrode, and a first drain electrode; a second transistor that includes an electron transit layer made of a nitride semiconductor, a second gate electrode, a second source electrode, and a second drain electrode; a sealing resin that covers the first transistor and the second transistor, first and second terminal at least partially exposed from the sealing resin, wherein the first gate electrode and the second drain electrode are directly connected to each other, and the first source electrode and the second source electrode are respectively directly connected to the first and second terminals; a first lead that is directly connected to the first source electrode and includes a first obverse surface and a first reverse surface that face mutually opposite sides in a thickness direction, wherein the sealing resin covers at least a portion of the first lead, and the first reverse surface is exposed from the sealing resin a second lead that is directly connected to the first drain electrode and is partially exposed from the sealing resin; a third lead that is directly connected to the first gate electrode and is partially exposed from the sealing resin; a fourth lead that is directly connected to the second gate electrode and is partially exposed from the sealing resin; and a fifth lead that is directly connected to the second source electrode and is partially exposed from the sealing resin. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the second lead is disposed opposite to the third lead, the fourth lead and the fifth lead with respect to the first lead as viewed in the thickness direction. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the fourth lead and the fifth lead are adjacent to each other. ### Claim 4 (depends on 2) The semiconductor device according to claim 2, wherein the first transistor further includes a third source electrode directly connected to the first source electrode, the semiconductor device further includes a sixth lead directly connected to the third source electrode and partially exposed from the sealing resin, and the sixth lead and the third lead are disposed on a same side of the first lead as viewed in the thickness direction. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the third lead and the sixth lead are adjacent to each other. ### Claim 6 (depends on 4) The semiconductor device according to claim 4, wherein the first transistor and the second transistor are monolithically integrated on a single semiconductor element, and the first gate electrode and the second drain electrode are directly connected to each other inside the semiconductor element. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein the semiconductor element includes an element obverse surface and an element reverse surface that face mutually opposite sides in the thickness direction, the element reverse surface is joined to the first obverse surface, the first gate electrode, the first source electrode, the first drain electrode, the second gate electrode, the second source electrode, and the third source electrode are disposed on the element obverse surface, and the first drain electrode is disposed opposite to the first gate electrode, the second gate electrode, the second source electrode and the third source electrode with respect to the first source electrode. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein the first drain electrode is offset toward the second lead with respect to the first source electrode, the third lead, the sixth lead, the fifth lead and the fourth lead are disposed in this order along a first direction perpendicular to the thickness direction, and the first gate electrode, the third source electrode, the second source electrode and the second gate electrode are disposed in this order along the first direction. ### Claim 9 (depends on 6) The semiconductor device according to claim 6, wherein the semiconductor element includes an element obverse surface and an element reverse surface that face mutually opposite sides in the thickness direction, the element reverse surface is joined to the first obverse surface, the first gate electrode, the first drain electrode, the second gate electrode, the second source electrode, and the third source electrode are disposed on the element obverse surface, and the first source electrode is disposed on the element reverse surface. ### Claim 10 (depends on 4) The semiconductor device according to claim 4, wherein the first transistor is formed as a first semiconductor element, and the second transistor is formed as a second semiconductor element that is separate from the first semiconductor element. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein the first transistor further includes a third gate electrode that is electrically connected to the first gate electrode inside the first semiconductor element and is disposed closer to the second semiconductor element than the first gate electrode is, and the third gate electrode and the second drain electrode are directly connected to each other. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, further comprising a bonding wire that is connected to the third gate electrode and the second drain electrode. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein a withstand voltage between the second drain electrode and the second source electrode of the second transistor is lower than a withstand voltage between the first drain electrode and the first source electrode of the first transistor. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein a distance between the first lead and the second lead is greater than a distance between the first lead and the third lead as viewed in the thickness direction. ### Claim 15 (depends on 4) The semiconductor device according to claim 4, further comprising a capacitor that is connected between the second source electrode and the third source electrode. ### Claim 16 (depends on 1) The semiconductor device according to claim 1, wherein the first transistor is a transistor that performs normally-off operations. ### Claim 17 (depends on 1) The semiconductor device according to claim 1, wherein the first transistor and the second transistor are High Electron Mobility Transistors (HEMTs) that use gallium nitride (GaN).