# US 11,444,007 B2 · Semiconductor device with galvanically isolated semiconductor chips > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,007 B2 - Document ID: US11444007B2 - Status: Granted - Kind: B2 - Application number: 16/907,739 - Filed: 2020-06-22 - Published: 2021-01-07 - Granted: 2022-09-13 - Earliest claimed: 2019-07-02 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Rainer Markus Schaller - Web page: https://patentgrep.com/patent/US11444007B2 ## CPC - H10W 70/421: {Shapes or dispositions} - H10W 70/413: {Insulating or insulated substrates serving as die pads (H10W70/468 takes precedence)} - H10W 70/415: {Leadframe inner leads serving as die pads} - H10W 70/417: {Bonding materials between chips and die pads} - H10W 70/442: {of multiple leadframes in a single chip} - H10W 70/458: {of insulating layers on leadframes} - H10W 70/69: Insulating materials thereof - H10W 74/10: characterised by their shape or disposition - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70) - H10W 90/00: Package configurations - H10W 90/811: {Multiple chips on leadframes} - H10W 72/381: {Auxiliary members} - H10W 72/536: {the connected ends being ball-shaped} - H10W 72/5363: {the connected ends being wedge-shaped} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/732: {between stacked chips} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/767: {between a chip and a laterally-adjacent lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a chip carrier, a first semiconductor chip arranged on the chip carrier, the first semiconductor chip being located in a first electrical potential domain when the semiconductor device is operated, a second semiconductor chip arranged on the chip carrier, the second semiconductor chip being located in a second electrical potential domain different from the first electrical potential domain when the semiconductor device is operated, and an electrically insulating structure arranged between the first semiconductor chip and the second semiconductor chip, which is designed to galvanically isolate the first semiconductor chip and the second semiconductor chip from each other. ## Claims ### Claim 1 A semiconductor device, comprising: a chip carrier located at a carrier electrical potential during operation of the semiconductor device; a first semiconductor chip arranged on the chip carrier, the first semiconductor chip being located in a first electrical potential domain during operation of the semiconductor device; a second semiconductor chip arranged on the chip carrier, the second semiconductor chip being located in a second electrical potential domain different from the first electrical potential domain when the semiconductor device is operated; and an electrically insulating structure arranged between the first semiconductor chip and the second semiconductor chip, which is configured to galvanically isolate the first semiconductor chip and the second semiconductor chip from each other, wherein the first electrical potential domain corresponds to a first operating voltage of the first semiconductor chip, wherein the second electrical potential domain corresponds to a second operating voltage of the second semiconductor chip, which is different from the first operating voltage, and wherein the carrier electrical potential is different from the first operating voltage and the second operating voltage. ### Claim 2 (depends on 1) The semiconductor device as claimed in claim 1, wherein the electrically insulating structure is free of alkaline-earth components. ### Claim 3 (depends on 1) The semiconductor device as claimed in claim 1, wherein the electrically insulating structure is free of plasticizers and solvents. ### Claim 4 (depends on 1) The semiconductor device as claimed in claim 1, wherein: the first electrical potential domain corresponds to a first ground potential, the first semiconductor chip being connected to the first ground potential, and the second electrical potential domain corresponds to a second ground potential different from the first ground potential, the second semiconductor chip being connected to the second ground potential. ### Claim 5 (depends on 1) The semiconductor device as claimed in claim 1, wherein: the first electrical potential domain corresponds to a first operating voltage of the first semiconductor chip, and the second electrical potential domain corresponds to a second operating voltage of the second semiconductor chip, which is different from the first operating voltage. ### Claim 6 (depends on 1) The semiconductor device as claimed in claim 1, further comprising: a chip fixing material arranged between the first semiconductor chip and the chip carrier. ### Claim 7 (depends on 1) The semiconductor device as claimed in claim 1, wherein the electrically insulating structure comprises a dielectric. ### Claim 8 (depends on 7) The semiconductor device as claimed in claim 7, wherein the dielectric comprises at least one of the following materials: ceramic, glass, or Kapton. ### Claim 9 (depends on 1) The semiconductor device as claimed in claim 1, wherein the electrically insulating structure is implemented as a surface coating of the first semiconductor chip. ### Claim 10 (depends on 9) The semiconductor device as claimed in claim 9, wherein the surface coating comprises at least one of the following materials: silicon oxide, silicon nitride, metal oxide, polymer, or polyimide. ### Claim 11 (depends on 1) The semiconductor device as claimed in claim 1, wherein the electrically insulating structure is vertically arranged between the first semiconductor chip and the chip carrier such that the electrically insulating structure is arranged on the chip carrier and the first semiconductor chip is arranged on the electrically insulating structure to form a stacked structure comprising the chip carrier, the electrically insulating structure, and the first semiconductor chip, wherein the electrically insulating structure is implemented as a surface coating of the chip carrier that is applied directly to a surface of the chip carrier, and wherein the electrically insulating structure has a one-piece integral construction. ### Claim 12 A semiconductor device, comprising: a chip carrier; a first semiconductor chip arranged on the chip carrier, the first semiconductor chip being located in a first electrical potential domain during operation of the semiconductor device; a second semiconductor chip arranged on the chip carrier, the second semiconductor chip being located in a second electrical potential domain different from the first electrical potential domain when the semiconductor device is operated; and an electrically insulating structure arranged between the first semiconductor chip and the second semiconductor chip, which is configured to galvanically isolate the first semiconductor chip and the second semiconductor chip from each other, wherein the electrically insulating structure is implemented as a surface coating of the chip carrier, and wherein the surface coating of the chip carrier comprises at least one of the following materials: parylene or metal oxide. ### Claim 13 (depends on 1) The semiconductor device as claimed in claim 1, wherein the electrically insulating structure is implemented as an encapsulation material, wherein at least one of the first semiconductor chip or the second semiconductor chip is encapsulated by the encapsulation material. ### Claim 14 (depends on 1) The semiconductor device as claimed in claim 1, wherein the electrically insulating structure is part of a routable molded lead frame. ### Claim 15 (depends on 1) The semiconductor device as claimed in claim 1, wherein the electrically insulating structure is arranged between the first semiconductor chip and the chip carrier, wherein the electrically insulating structure is arranged on the chip carrier and the first semiconductor chip is arranged on the electrically insulating structure to form a first stacked structure comprising the chip carrier, the electrically insulating structure, and the first semiconductor chip. ### Claim 16 (depends on 15) The semiconductor device as claimed in claim 15, further comprising: a further electrically insulating structure arranged between the second semiconductor chip and the chip carrier, wherein the further electrically insulating structure is arranged on the chip carrier and the second semiconductor chip is arranged on the further electrically insulating structure to form a second stacked structure comprising the chip carrier, the further electrically insulating structure, and the second semiconductor chip. ### Claim 17 (depends on 1) The semiconductor device as claimed in claim 1, wherein: the first semiconductor chip and the second semiconductor chip are arranged on the same surface of the chip carrier, and the first semiconductor chip and the second semiconductor chip are stacked on top of each other. ### Claim 18 (depends on 1) The semiconductor device as claimed in claim 1, wherein the first semiconductor chip and the second semiconductor chip each comprise a sensor chip. ### Claim 19 (depends on 1) The semiconductor device as claimed in claim 1, wherein the first semiconductor chip and the second semiconductor chip form a coupler. ### Claim 20 (depends on 1) The semiconductor device as claimed in claim 1, wherein: the first semiconductor chip comprises a power semiconductor chip, and the second semiconductor chip comprises a logic semiconductor chip. ### Claim 21 (depends on 1) The semiconductor device as claimed in claim 1, wherein the carrier electrical potential is a floating voltage having a value between the first operating voltage and the second operating voltage. ### Claim 22 (depends on 1) The semiconductor device as claimed in claim 1, further comprising: an encapsulation material that encapsulates the first semiconductor chip, the second semiconductor chip, the chip carrier, and the electrically insulating structure, wherein the electrically insulating structure is implemented as the surface coating of the chip carrier that is applied directly to a surface of the chip carrier and is separate from the encapsulation material, wherein the electrically insulating structure is vertically arranged between the first semiconductor chip and the chip carrier such that the electrically insulating structure is arranged on the chip carrier and the first semiconductor chip is arranged on the electrically insulating structure to form a stacked structure comprising the chip carrier, the electrically insulating structure, and the first semiconductor chip. ### Claim 23 (depends on 22) The semiconductor device as claimed in claim 22, wherein the electrically insulating structure is arranged between the encapsulation material and the chip carrier. ### Claim 24 (depends on 23) The semiconductor device as claimed in claim 23, wherein the electrically insulating structure encapsulates the chip carrier. ### Claim 25 (depends on 11) The semiconductor device as claimed in claim 11, wherein the electrically insulating structure encapsulates the chip carrier. ### Claim 26 (depends on 16) The semiconductor device as claimed in claim 16, wherein the chip carrier is vertically arranged between the electrically insulating structure and the further electrically insulating structure. ### Claim 27 (depends on 16) The semiconductor device as claimed in claim 16, wherein: the first stacked structure comprises a first chip fixing material arranged between the first semiconductor chip and the chip carrier, and the second stacked structure comprises a second chip fixing material arranged between the second semiconductor chip and the chip carrier. ### Claim 28 (depends on 27) The semiconductor device as claimed in claim 27, wherein: the first stacked structure comprises a third chip fixing material arranged between the electrically insulating structure and the first semiconductor chip, and the second stacked structure comprises a fourth chip fixing material arranged between the further electrically insulating structure and the second semiconductor chip. ### Claim 29 (depends on 16) The semiconductor device as claimed in claim 16, wherein the electrically insulating structure and the further electrically insulating structure both have a respective one-piece integral construction. ### Claim 30 (depends on 16) The semiconductor device as claimed in claim 16, further comprising: an encapsulation material that encapsulates the first semiconductor chip, the second semiconductor chip, the chip carrier, the electrically insulating structure, and the further electrically insulating structure, wherein the electrically insulating structure and the further electrically insulating structure are separate from the encapsulation material.