# US 11,444,001 B1 · Thermoelectric semiconductor device and method of making same

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- Number: US 11,444,001 B1
- Document ID: US11444001B1
- Status: Granted
- Kind: B1
- Application number: 17/314,712
- Filed: 2021-05-07
- Granted: 2022-09-13
- Earliest claimed: 2021-05-07
- Assignees: Western Digital Technologies, Inc.
- Applicants: Western Digital Technologies, Inc.
- Inventors: Jiandi Du; Yazhou Zhang; Binbin Zheng; Sundarraj Chandran; Wenbin Qu; Chin-Tien Chiu
- Web page: https://patentgrep.com/patent/US11444001B1

## CPC

- H10W 40/28: comprising Peltier coolers
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A thermoelectric semiconductor device includes a heat dissipating semiconductor module and a stack of flash memory dies mounted on a substrate. The heat dissipating module comprises a first semiconductor die such as a controller, and a second semiconductor die such as a thermoelectric semiconductor die to cool the first semiconductor die during operation. The thermoelectric semiconductor die may be mounted to the controller die at the wafer level.

## Claims

### Claim 1

A method of forming heat dissipating semiconductor modules, comprising the steps of:
forming a first group of semiconductor dies on a first wafer by the step of forming integrated circuits and metallization layers in a first major surface of the first wafer in areas defining the first group of semiconductor dies;
forming a second group of semiconductor dies on a second wafer, the second group of semiconductor dies being thermoelectric semiconductor dies, by the step of doping p-n regions at least in areas of the second wafer defining the second group of semiconductor dies such that a temperature gradient or voltage potential between first and second surfaces of a semiconductor die of the second group of semiconductor dies results in migration of charge carriers between the first and second surfaces of the semiconductor die; and
the first and second groups of semiconductor dies on the first and second wafers formed such that the first group of semiconductor dies align with the second group of semiconductor dies upon joining of the first and second semiconductor wafers to form the heat dissipating semiconductor modules.

### Claim 2 (depends on 1)

The method of claim 1, wherein said steps of forming the first and second groups of semiconductor dies further comprises the step of forming a semiconductor die from the first group to a same size as a semiconductor die of the second group.

### Claim 3 (depends on 1)

The method of claim 1, wherein said step of forming the first group of semiconductor dies comprises the step of forming the first group of semiconductor dies into controller dies.

### Claim 4 (depends on 1)

The method of claim 1, wherein said step of forming the group of second semiconductor dies comprises the step of configuring a second semiconductor die to have a voltage potential between first and second surfaces of the semiconductor die upon connecting the heat dissipating semiconductor module to an electrical circuit and heating of the first semiconductor die.

### Claim 5 (depends on 1)

The method of claim 1, wherein said step of forming the second group of semiconductor dies comprises the step of configuring a semiconductor die of the second group to have a temperature gradient between first and second surfaces of the semiconductor die upon connecting the heat dissipating semiconductor module to an electrical circuit and running a current through the electrical circuit.

### Claim 6

A method of forming a thermoelectric semiconductor device, comprising the steps of:
receiving a first wafer including a group of first semiconductor dies, the first semiconductor dies comprising integrated circuits having metallization layers in a first major surface of the first wafer in areas defining the first group of semiconductor dies;
receiving a second wafer including a group of second semiconductor dies, the second semiconductor dies comprising thermoelectric semiconductor dies formed by doping p-n regions at least in areas of the second wafer defining the second semiconductor dies such that a temperature gradient or voltage potential between first and second surfaces of a second semiconductor die results in migration of charge carriers between the first and second surfaces thereof; and
joining the first and second semiconductor wafers, the first and second semiconductor dies on the first and second wafers being aligned, to form heat dissipating semiconductor modules.

### Claim 7 (depends on 6)

The method of claim 6, further comprising the step of dicing the heat dissipating semiconductor modules.

### Claim 8 (depends on 7)

The method of claim 7, further comprising the step of forming a first electrical conductor on a first major surface of the second wafer at least in the areas of the second wafer defining the group of second semiconductor dies.

### Claim 9 (depends on 8)

The method of claim 8, further comprising the step of forming a second conductive layer on the second semiconductor wafer on a second major surface opposite the first major surface.

### Claim 10 (depends on 9)

The method of claim 9, said step of forming the second conductive layer on the second major surface of the second semiconductor wafer occurring after said step of dicing the heat dissipating semiconductor modules from the affixed first and second semiconductor wafers.

### Claim 11 (depends on 6)

The method of claim 6, further comprising the step of backgrinding a second major surface of the first semiconductor wafer, opposite the first major surface of the first semiconductor wafer, prior to affixing the first and second semiconductor wafers.

### Claim 12 (depends on 11)

The method of claim 11, further comprising the step of forming bump bonds on the second major surface of the first semiconductor die after said step of backgrinding the second major surface of the first semiconductor die.

### Claim 13 (depends on 6)

The method of forming a thermoelectric semiconductor device of claim 6, further comprising the steps of:
attaching a heat dissipating semiconductor module to a substrate;
electrically coupling the first semiconductor die of the heat dissipating semiconductor module to the substrate; and
electrically coupling the second semiconductor die of the heat dissipating semiconductor module to the substrate.

### Claim 14 (depends on 13)

The method of claim 13, wherein said step of electrically coupling the first semiconductor die to the substrate comprises the step of flip-chip bonding the first semiconductor die to a first set of contact pads on the substrate.

### Claim 15 (depends on 14)

The method of claim 14, wherein said step of electrically coupling the second semiconductor die to the substrate comprises the step of wire bonding the second semiconductor die to a second set of contact pads on the substrate.

### Claim 16 (depends on 13)

The method of claim 13, further comprising the step of attaching and electrically coupling one or more flash memory dies to the substrate.

### Claim 17 (depends on 16)

The method of claim 16, wherein the one or more flash memory dies are stacked one upon another and the stack is positioned adjacent to the heat dissipating semiconductor module.

### Claim 18

A method of forming a thermoelectric semiconductor device, comprising the steps of:
attaching a heat dissipating semiconductor module to a substrate, the heat dissipating semiconductor module formed by affixing a first wafer comprising controller dies to a second wafer comprising thermoelectric semiconductor dies and dicing the first and second wafer assembly such that the controller dies attach to the thermoelectric semiconductor dies to form a plurality of heat dissipating semiconductor modules including the heat dissipating semiconductor module, wherein the thermoelectric semiconductor die is doped with p-n regions such that a temperature gradient or voltage potential between first and second surfaces of the thermoelectric semiconductor die results in cooling of the controller die;
attaching one or more flash memory dies to the substrate adjacent to the heat dissipating semiconductor module;
electrically coupling the heat dissipating semiconductor module to the substrate; and
electrically coupling the one or more flash memory dies to the substrate, wherein the substrate facilitates electrical communication between the controller die and the one or more flash memory dies.

### Claim 19 (depends on 18)

The method of claim 18, said step of electrically coupling the heat dissipating semiconductor module to the substrate comprising the step of electrically coupling bump bonds on a surface of the controller die to contact pads on the substrate.

### Claim 20 (depends on 18)

The method of claim 18, the contact pads comprising a first set of contact pads, said step of electrically coupling the heat dissipating semiconductor module to the substrate further comprising the step of electrically coupling a surface of the thermoelectric semiconductor die to a second set of contact pads on the substrate.