# US 11,443,997 B2 · Semiconductor package and method of manufacturing the same

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- Number: US 11,443,997 B2
- Document ID: US11443997B2
- Status: Granted
- Kind: B2
- Application number: 16/933,806
- Filed: 2020-07-20
- Published: 2022-01-20
- Granted: 2022-09-13
- Earliest claimed: 2020-07-20
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Advanced Semiconductor Engineering, Inc.
- Inventors: Wei Chih Cho; Chun Chen Chen; Shao-Lun Yang
- Web page: https://patentgrep.com/patent/US11443997B2

## CPC

- H10W 70/611: {for connecting multiple chips together}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/01: Manufacture or treatment
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/728: {between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a first substrate, a second substrate, and a barrier structure. The first substrate has a first surface and a second surface opposite to the first surface. The second substrate has a first surface facing the second surface of the first substrate. The first substrate electrically bonds to the second substrate through a conductive terminal disposed between the second surface of the first substrate and the first surface of the second substrate. The barrier structure is disposed adjacent to the first surface of the first substrate.

## Claims

### Claim 1

A semiconductor package, comprising:
a first substrate, having a first surface and a second surface opposite to the first surface;
a second substrate, having a first surface facing the second surface of the first substrate, wherein the first substrate electrically bonds to the second substrate through a conductive terminal disposed between the second surface of the first substrate and the first surface of the second substrate;
a barrier structure disposed adjacent to the first surface of the first substrate;
a first molding layer disposed between the first substrate and the second substrate, wherein the first molding layer extends from the first surface of the second substrate to the first surface of the first substrate and covers at least a portion of the first surface of the first substrate; and
a second molding layer disposed adjacent to the first surface of the first substrate,
wherein the first molding layer connects to the second molding layer at an interface, wherein the interface is within the range from the first surface of the first substrate to a top portion of the barrier structure.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the barrier structure surrounds an electrical connection area of the first surface of the first substrate.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the first molding layer extends from the first surface of the second substrate to a side surface of the first substrate.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein the first molding layer reaches the barrier structure.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein the first substrate has a projection area smaller than that of the second substrate.

### Claim 6 (depends on 5)

The semiconductor package of claim 5, wherein the interface is within the range from the second surface of the first substrate to the top portion of the barrier structure.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, further comprising a recess disposed adjacent to the first surface of the first substrate and adjacent to the barrier structure.

### Claim 8 (depends on 7)

The semiconductor package of claim 7, wherein the barrier structure surrounds the recess.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein a side surface of the first substrate and a side surface of the second substrate are exposed from the first molding layer.

### Claim 10 (depends on 1)

The semiconductor package of claim 1, wherein the interface is substantially equal to or below the barrier structure.

### Claim 11 (depends on 1)

The semiconductor package of claim 1, further comprising a first electronic component disposed adjacent to the second surface of the first substrate and a second electronic component disposed adjacent to the first surface of the first substrate.

### Claim 12 (depends on 1)

The semiconductor package of claim 1, wherein the barrier structure is disposed adjacent to an edge of the first substrate.

### Claim 13 (depends on 1)

The semiconductor package of claim 1, wherein the barrier structure is disposed along an edge of the first substrate.

### Claim 14 (depends on 1)

The semiconductor package of claim 1, wherein the barrier structure comprises a plurality of walls toward the same direction.

### Claim 15 (depends on 1)

The semiconductor package of claim 1, wherein the barrier structure is a single wall.

### Claim 16 (depends on 7)

The semiconductor package of claim 7, wherein the recess is disposed between the barrier structure and an electrical connection area of the first surface of the first substrate.