# US 11,443,995 B2 · Integrated circuit package and method

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- Number: US 11,443,995 B2
- Document ID: US11443995B2
- Status: Granted
- Kind: B2
- Application number: 17/120,859
- Filed: 2020-12-14
- Published: 2021-04-01
- Granted: 2022-09-13
- Earliest claimed: 2018-09-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chen-Hua Yu; Sung-Feng Yeh; Ming-Fa Chen; Hsien-Wei Chen; Tzuan-Horng Liu
- Web page: https://patentgrep.com/patent/US11443995B2

## CPC

- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/42: Vias, e.g. via plugs
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 90/00: Package configurations
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/853: {On the same surface}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

## Claims

### Claim 1

A method comprising:
hybrid bonding a first die to a second die;
after hybrid bonding the first die to the second die, depositing a seed layer over a top surface of the first die;
plating a plurality of thermal vias on the seed layer and the top surface of first die;
encapsulating the first die, the second die, and the plurality of thermal vias in an encapsulant;
planarizing the encapsulant to expose the plurality of thermal vias; and
forming a redistribution structure electrically connected to the first die and the second die.

### Claim 2 (depends on 1)

The method of claim 1, wherein depositing the seed layer further comprises depositing the seed layer over and along sidewalls of the second die.

### Claim 3 (depends on 1)

The method of claim 1 further comprising:
prior to hybrid bonding the first die to the second die, attaching the first die to a carrier, wherein the seed layer is deposited over the carrier; and
plating a plurality of through vias on the seed layer and a top surface of the carrier.

### Claim 4 (depends on 1)

The method of claim 1 further comprising:
prior to forming the redistribution structure, removing the first die and the second die from a first carrier; and
attaching a second carrier to a side of the second die opposite the first die, wherein the redistribution structure is formed on an opposing side of the first die as the second die.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming the redistribution structure comprises forming the redistribution structure on an opposing side of the second die as the first die.

### Claim 6 (depends on 5)

The method of claim 5 further comprising depositing a passivation layer between the seed layer and the first die, wherein the passivation layer is further deposited over and along sidewalls of the second die.

### Claim 7 (depends on 6)

The method of claim 6 further comprising forming a contact pad over the passivation layer, wherein the redistribution structure is electrically connected to the second die through the contact pad.

### Claim 8 (depends on 1)

The method of claim 1 further comprising after plating the plurality of thermal vias, removing portions of the seed layer not covered by the plurality of thermal vias.

### Claim 9 (depends on 1)

The method of claim 1, wherein depositing the seed layer further comprises depositing the seed layer along sidewalls of the first die.

### Claim 10

A method comprising:
directly bonding a first insulating layer of a first die to a second insulating layer of a second die;
depositing a passivation layer over and along sidewalls of the second die and over a top surface of the first die;
forming a plurality of thermal vias over the passivation layer and adjacent the second die, wherein the passivation layer separates the plurality of thermal vias from the first die;
encapsulating the first die, the second die, and the plurality of thermal vias in an encapsulant; and
forming a redistribution structure over the encapsulant, the first die, and the second die.

### Claim 11 (depends on 10)

The method of claim 10 further comprising forming a plurality of contact pads over the passivation layer and electrically connected to the second die, wherein the plurality of contact pads interpose the redistribution structure and the second die.

### Claim 12 (depends on 11)

The method of claim 11, wherein forming the plurality of contact pads comprises forming the plurality of contact pads prior to forming the plurality of thermal vias.

### Claim 13 (depends on 10)

The method of claim 10 further comprising forming a plurality of through vias adjacent the first die, wherein the encapsulant encapsulates the plurality of through vias.

### Claim 14 (depends on 13)

The method of claim 13 further comprising forming a plurality of conductive connectors on the plurality of through vias, wherein the plurality of through vias electrically connect the plurality of conductive connectors the redistribution structure.

### Claim 15 (depends on 10)

The method of claim 10, wherein the second die comprises:
a semiconductor substrate; and
a plurality of through substrate vias (TSVs) extending through the semiconductor substrate, wherein depositing the passivation layer comprises depositing the passivation layer around portions of the plurality of TSVs that extend above the semiconductor substrate.

### Claim 16

A method comprising:
directly bonding a first die to a second die;
depositing a seed layer over a backside of the first die;
plating a plurality of thermal vias on the seed layer, the plurality of thermal vias being adjacent to the second die;
encapsulating the first die, the second die, and the plurality of thermal vias in an encapsulant; and
forming a redistribution structure on an opposing side of the first die as the second die.

### Claim 17 (depends on 16)

The method of claim 16, wherein directly bonding the first die to the second die comprises:
directly bonding a first insulating layer of the first die to a second insulating layer of the second die; and
directly bonding a first conductive feature of the first die to a second conductive feature of the second die.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first conductive feature of the first die a through substrate via (TSV) of the first die.

### Claim 19 (depends on 16)

The method of claim 16, wherein depositing the seed layer further comprises depositing the seed layer over and along sidewalls of the second die.

### Claim 20 (depends on 16)

The method of claim 16 further comprising plating a plurality of through vias on the seed layer while plating the plurality of thermal vias, wherein the plurality of through vias are adjacent to the first die.