# US 11,443,989 B2 · Array substrate, display panel, method of fabricating display panel, and mother substrate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,989 B2 - Document ID: US11443989B2 - Status: Granted - Kind: B2 - Application number: 16/498,777 - Filed: 2019-05-08 - Published: 2021-12-30 - Granted: 2022-09-13 - Earliest claimed: 2018-11-16 - Assignees: Hefei Boe Display Technology Co., Ltd.; Beijing BOE Technology Development Co., Ltd. - Applicants: Hefei BOE Display Technology Co., Ltd.; BOE Technology Group Co., Ltd. - Inventors: Ke Dai; Peng Jiang; Yanping Liao; Wenchao Wang - Web page: https://patentgrep.com/patent/US11443989B2 ## CPC - H10D 86/443: {adapted for preventing breakage, peeling or short circuiting} - H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads} - G02F 1/1309: {Repairing; Testing} - G02F 1/13452: {Conductors connecting driver circuitry and terminals of panels} - G02F 1/1362: Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} - G02F 1/136254: {Checking; Testing} - H10D 86/021: {of multiple TFTs} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/60: wherein the TFTs are in active matrices - H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects} - G02F 1/136263: {Line defects} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An array substrate having a display area, a peripheral area, and a bonding area inside the peripheral area is provided. The array substrate includes a bonding pad in the bonding area, the bonding pad configured to be connected to a peripheral circuit through a bonding connector, a test signal line including a first portion and a second portion. The first portion is in the peripheral area and substantially surrounds the display area. The first portion is electrically connected to the bonding pad. The first portion is completely inside the array substrate and has no exposed terminal. The second portion is in the bonding area. A first terminal of the second portion is electrically connected to the bonding pad. A second terminal of the second portion has an end along an edge of the array substrate in the bonding area. ## Claims ### Claim 1 An array substrate having a display area, a peripheral area, and a bonding area inside the peripheral area, comprising: a bonding pad in the bonding area, the bonding pad configured to be connected to a peripheral circuit through a bonding connector; a test signal line comprising a first portion and a second portion; wherein the first portion is in the peripheral area and substantially surrounds the display area; the first portion is electrically connected to the bonding pad; the first portion is completely inside the array substrate and has no exposed terminal; the second portion is in the bonding area; a first terminal of the second portion is electrically connected to the bonding pad; and a second terminal of the second portion has an end along an edge of the array substrate in the bonding area. ### Claim 2 (depends on 1) The array substrate of claim 1, further comprising a plurality of data lines extending along a direction from the bonding area to a side of the array substrate opposite to the bonding area; wherein the test signal line is an array data pad opposite data (ADD) line for detecting defects in the plurality of data lines of the array substrate. ### Claim 3 (depends on 2) The array substrate of claim 2, wherein the test signal line is electrically connected to the plurality of data lines on the side of the array substrate opposite to the bonding area. ### Claim 4 (depends on 3) The array substrate of claim 3, further comprising a plurality of electrostatic discharge shorting structures on the side of the array substrate opposite to the bonding area; wherein the test signal line is electrically connected to the plurality of data lines respectively through the plurality of electrostatic discharge shorting structures. ### Claim 5 (depends on 2) The array substrate of claim 2, wherein the test signal line and the plurality of data lines are in a same layer and comprise a same material. ### Claim 6 (depends on 1) The array substrate of claim 1, further comprising a plurality of gate lines extending along a direction from a first lateral side of the array substrate to a second lateral side of the array substrate, the first lateral side and the second lateral side respectively connecting a side of the array substrate having the bonding area and a side of the array substrate opposite to the bonding area; wherein the array substrate is absent of any exposed ends of the test signal line along edges of the first lateral side and the second lateral side of the array substrate. ### Claim 7 (depends on 6) The array substrate of claim 6, wherein the test signal line and the plurality of gate lines are in a same layer and comprise a same material. ### Claim 8 (depends on 1) The array substrate of claim 1, further comprising a ground voltage line and a common voltage signal line in the peripheral area; wherein the test signal line does not cross over the ground voltage line and does not cross over the common voltage signal line. ### Claim 9 (depends on 1) The array substrate of claim 1, wherein the end of the second terminal of the second portion is configured to be covered by the bonding connector. ### Claim 10 (depends on 1) A display panel, comprising the array substrate of claim 1; a counter substrate facing the array substrate; the bonding connector connected to the bonding pad; a peripheral circuit connected to the bonding pad through the bonding connector; a data driving circuit in the bonding area; and a gate driving circuit in the bonding area. ### Claim 11 (depends on 10) The display panel of claim 10, wherein the bonding connector comprises a flexible protective film and a bonding connection line protected by the flexible protective film. ### Claim 12 A method of fabricating an array substrate having a display area, a peripheral area, and a bonding area inside the peripheral area, comprising: forming a bonding pad in the bonding area, the bonding pad configured to be connected to a peripheral circuit through a bonding connector; forming a test signal line comprising a first portion and a second portion; wherein the first portion is formed in the peripheral area and substantially surrounds the display area; the first portion is electrically connected to the bonding pad; the first portion is completely inside the array substrate and has no exposed terminal; the second portion is formed in the bonding area; a first terminal of the second portion is electrically connected to the bonding pad; and a second terminal of the second portion has an end along an edge of the array substrate in the bonding area. ### Claim 13 (depends on 12) The method of claim 12, comprising: forming a mother substrate having a plurality of substrate regions and a cutting region spacing apart the plurality of substrate regions, wherein components of the array substrate are formed in a respective one of the plurality of substrate regions; cutting the mother substrate along a border between the respective one of the plurality of substrate regions and the cutting region, thereby forming the array substrate. ### Claim 14 (depends on 13) The method of claim 13, wherein forming the mother substrate comprises: forming an array substrate in a respective one of the plurality of substrate regions; and forming a testing pad in the cutting region; wherein the array substrate has a display area, a peripheral area, and a bonding area inside the peripheral area; wherein forming the array substrate comprises: forming a bonding pad in the bonding area, the bonding pad configured to be connected to a peripheral circuit through a bonding connector; forming a test signal line comprising a first portion and a third portion; wherein the first portion is formed in the peripheral area and substantially surrounds the display area; the first portion is electrically connected to the bonding pad; the first portion is completely inside the array substrate and has no exposed terminal; the third portion extends from the bonding area into the cutting region to connect to the testing pad; a first terminal of the third portion is electrically connected to the bonding pad; and a second terminal of the third portion is electrically connected to the testing pad. ### Claim 15 (depends on 14) The method of claim 14, wherein forming the array substrate further comprises forming a plurality of data lines extending along a direction from the bonding area to a side of the array substrate opposite to the bonding area; wherein, subsequent to forming the mother substrate and prior to cutting the mother substrate, the method further comprises transmitting a test signal to the test signal line through the testing pad to detect defects in the plurality of data lines of the array substrate. ### Claim 16 (depends on 14) The method of claim 14, wherein cutting the mother substrate along the border between the respective one of the plurality of substrate regions and the cutting region cuts the third portion along an edge of the array substrate in the bonding area, thereby forming the second portion; a first terminal of the second portion is electrically connected to the bonding pad; and a second terminal of the second portion has an end along the edge of the array substrate in the bonding area; and the end of the second terminal of the second portion is configured to be covered by the bonding connector. ### Claim 17 (depends on 14) The method of claim 14, subsequent to cutting the mother substrate, further comprising applying a protective adhesive layer to cover the end of the second terminal of the second portion. ### Claim 18 (depends on 12) The method of claim 12, wherein the end of the second terminal of the second portion is covered by the bonding connector. ### Claim 19 (depends on 15) A method of fabricating a display panel, comprising the method of fabricating the array substrate of claim 15; connecting the bonding connector to the bonding pad, wherein the end of the second terminal of the second portion is covered by the bonding connector; connecting a peripheral circuit to the bonding pad through the bonding connector; providing a counter substrate facing the array substrate; and assembling the array substrate and the counter substrate into a cell. ### Claim 20 A mother substrate having a plurality of substrate regions and a cutting region spacing apart the plurality of substrate regions, comprising: an array substrate in a respective one of the plurality of substrate regions; and a testing pad in the cutting regions; wherein the array substrate has a display area, a peripheral area, and a bonding area inside the peripheral area; wherein the array substrate comprises: a bonding pad in the bonding area, the bonding pad configured to be connected to a peripheral circuit through a bonding connector; a test signal line comprising a first portion and a third portion; wherein the first portion is in the peripheral area and substantially surrounds the display area; the first portion is electrically connected to the bonding pad; the first portion is completely inside the array substrate and has no exposed terminal; the third portion extends from the bonding area into the cutting region to connect to the testing pad; a first terminal of the third portion is electrically connected to the bonding pad; and a second terminal of the third portion is electrically connected to the testing pad.