# US 11,443,987 B2 · Semiconductor devices with backside air gap dielectric

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- Number: US 11,443,987 B2
- Document ID: US11443987B2
- Status: Granted
- Kind: B2
- Application number: 16/888,217
- Filed: 2020-05-29
- Published: 2021-12-02
- Granted: 2022-09-13
- Earliest claimed: 2020-05-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chun-Yuan Chen; Huan-Chieh Su; Cheng-Chi Chuang; Yu-Ming Lin; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US11443987B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6682: {the compound being a silane, e.g. disilane, methylsilane or chlorosilane}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 95/062: {involving a dielectric removal step}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/43: Layouts of interconnections
- H10W 20/46: comprising air gaps
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/427: {Power or ground buses}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes providing a structure having transistors, an isolation structure over the transistors, metal plugs through the isolation structure and connecting to the transistors, and a trench with the isolation structure and the metal plugs as sidewalls. The method further includes forming a dielectric liner on the sidewalls of the trench and over the isolation structure and the metal plugs. The dielectric liner is thicker at an opening portion of the trench than at another portion of the trench so that an air gap is formed inside the trench and the air gap is surrounded by the dielectric liner. The method further includes depositing a sacrificial layer over the dielectric liner and over the air gap and performing CMP to remove the sacrificial layer and to recess the dielectric liner until the isolation structure and the metal plugs are exposed. The air gap remains inside the trench.

## Claims

### Claim 1

A method, comprising:
providing a structure having transistors, an isolation structure that is at least partially over the transistors, two metal plugs through the isolation structure and electrically connecting to electrodes of the transistors, and a trench, wherein the isolation structure and the two metal plugs form sidewalls of the trench;
forming a dielectric liner on the sidewalls of the trench and over the isolation structure and the metal plugs, wherein the dielectric liner is thicker at an opening portion of the trench than at another portion of the trench that is deeper than the opening portion so that an air gap is formed inside the trench and the air gap is fully or partially surrounded by the dielectric liner;
depositing a sacrificial dielectric layer over the dielectric liner and over the air gap; and
performing a chemical-mechanical planarization (CMP) process to remove the sacrificial dielectric layer and to recess the dielectric liner until the isolation structure and the metal plugs are exposed, wherein the air gap remains inside the trench.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a dielectric layer over the isolation structure, the dielectric liner, the air gap, and the metal plugs, wherein the air gap is sealed by the dielectric liner alone or by both the dielectric liner and the dielectric layer; and
forming conductors in the dielectric layer, wherein the conductors are electrically connected to the metal plugs.

### Claim 3 (depends on 1)

The method of claim 1, wherein the forming of the dielectric liner includes using plasma enhanced chemical vapor deposition (PECVD).

### Claim 4 (depends on 3)

The method of claim 3, wherein the PECVD includes applying plasma generated from SiH4 gas and N2 or NH3 gas.

### Claim 5 (depends on 1)

The method of claim 1, before the forming of the dielectric liner, further comprising:
treating the sidewalls of the trench with a plasma having atoms of nitrogen, fluorine, chlorine, oxygen, hydrogen, or argon.

### Claim 6 (depends on 1)

The method of claim 1, wherein the providing of the structure includes:
receiving a workpiece having a substrate with active regions, wherein the isolation structure isolates the active regions, and the transistors are formed over the active regions, the workpiece further having an interconnect structure over the transistors, wherein the substrate is at a backside of the workpiece and the interconnect structure is at a frontside of the workpiece;
attaching the frontside of the workpiece to a carrier wafer;
thinning the workpiece from the backside of the workpiece until the isolation structure and the active regions are exposed from the backside of the workpiece;
etching two holes through the active regions to expose the electrodes of the transistors from the backside of the workpiece;
forming the two metal plugs in the two holes respectively; and
etching the active regions between the two metal plugs from the backside of the workpiece, thereby forming the trench.

### Claim 7 (depends on 6)

The method of claim 6, wherein the transistors include FinFETs and the active regions include semiconductor fins.

### Claim 8 (depends on 6)

The method of claim 6, wherein the transistors include gate-all-around FETs and the active regions include semiconductor fins.

### Claim 9 (depends on 1)

The method of claim 1, wherein the trench is as deep as or deeper than the metal plugs.

### Claim 10

A method, comprising:
providing a structure having a silicon substrate, an isolation structure over the silicon substrate, one or more semiconductor fins extending from the silicon substrate and over the isolation structure, one or more transistors formed over the one or more semiconductor fins, and an interconnect structure over the one or more transistors, wherein the silicon substrate is at a backside of the structure and the interconnect structure is at a frontside of the structure;
attaching the frontside of the structure to a carrier substrate;
thinning the structure from the backside of the structure until the isolation structure and the one or more semiconductor fins are exposed from the backside of the structure;
etching two holes through the one or more semiconductor fins to expose two source/drain features of the one or more transistors from the backside of the structure;
forming two metal plugs in the two holes respectively;
etching the one or more semiconductor fins between the two metal plugs from the backside of the structure, thereby forming a trench; and
forming a dielectric liner on sidewalls of the trench and over the isolation structure and the metal plugs, wherein the dielectric liner is thicker at an opening portion of the trench than at another portion of the trench that is deeper than the opening portion so that an air gap is formed inside the trench.

### Claim 11 (depends on 10)

The method of claim 10, wherein the trench is as deep as or deeper than the metal plugs from the backside of the structure.

### Claim 12 (depends on 10)

The method of claim 10, wherein the air gap is fully surrounded by the dielectric liner alone.

### Claim 13 (depends on 10)

The method of claim 10, further comprising:
depositing a sacrificial dielectric layer over the dielectric liner and over the air gap; and
performing a chemical-mechanical planarization (CMP) process to remove the sacrificial dielectric layer and to recess the dielectric liner until the isolation structure and the metal plugs are exposed, wherein the air gap remains inside the trench.

### Claim 14 (depends on 13)

The method of claim 13, after the performing of the CMP process, further comprising:
forming another interconnect structure over the backside of the structure and over the dielectric liner, the air gap, and the metal plugs.

### Claim 15 (depends on 10)

The method of claim 10, wherein the forming of the dielectric liner includes using plasma enhanced chemical vapor deposition (PECVD) with plasma generated from SiH4 gas and NH3 gas.

### Claim 16

A method, comprising:
providing a structure having a substrate, an isolation structure over the substrate, one or more semiconductor fins extending from the substrate and above the isolation structure, one or more transistors formed over the one or more semiconductor fins, wherein the substrate is at a backside of the structure and the one or more transistors are at a frontside of the structure;
thinning the structure from the backside of the structure until the isolation structure and the one or more semiconductor fins are exposed from the backside of the structure;
etching two holes through the one or more semiconductor fins to expose two source/drain features of the one or more transistors from the backside of the structure;
forming two metal plugs in the two holes respectively;
selectively etching the one or more semiconductor fins between the two metal plugs from the backside of the structure, thereby forming a trench;
forming a dielectric liner on sidewalls of the trench and over the isolation structure and the metal plugs, wherein the dielectric liner is thicker at an opening portion of the trench than at another portion of the trench that is deeper than the opening portion;
depositing a sacrificial dielectric layer covering the dielectric liner; and
performing a chemical-mechanical planarization (CMP) process to remove the sacrificial dielectric layer and to recess the dielectric liner until the isolation structure and the metal plugs are exposed.

### Claim 17 (depends on 16)

The method of claim 16, wherein the forming of the dielectric liner also forms an air gap inside the trench, and the sacrificial dielectric layer is deposited to cover the air gap without completely filling the air gap.

### Claim 18 (depends on 17)

The method of claim 17, after performing the CMP process, further comprising:
forming a second dielectric layer on the backside of the structure, wherein the air gap is sealed by the dielectric liner alone or by both the dielectric liner and the second dielectric layer.

### Claim 19 (depends on 16)

The method of claim 16, wherein the trench is deeper than the metal plugs from the backside of the structure.

### Claim 20 (depends on 16)

The method of claim 16, wherein the forming of the dielectric liner includes using plasma enhanced chemical vapor deposition (PECVD) that applies plasma generated from SiH4 gas and N2 or NH3 gas.