# US 11,443,986 B2 · Method for making semiconductor device by adopting stress memorization technique

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- Number: US 11,443,986 B2
- Document ID: US11443986B2
- Status: Granted
- Kind: B2
- Application number: 17/147,984
- Filed: 2021-01-13
- Published: 2021-10-28
- Granted: 2022-09-13
- Earliest claimed: 2020-04-26
- Assignees: Shanghai Huali Integrated Circuit Corporation
- Applicants: Shanghai Huali Integrated Circuit Corporation
- Inventors: Weiwei Ma; Chao Sun; Wei Lu; Xiaolin Xu; Yamin Cao; Wei Zhou
- Web page: https://patentgrep.com/patent/US11443986B2

## CPC

- H10D 30/796: {having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0167: {Manufacturing their channels}
- H10P 14/6304: {Formation by oxidation, e.g. oxidation of the substrate}
- H10P 14/6903: {containing silicon}
- Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

The application discloses a method of applying the stress memorization technique in making the semiconductor device which includes: step 1: forming a front gate structure on a silicon wafer having front and back surfaces; step 2: forming sidewalls including a first silicon nitride sidewall, a first silicon nitride layer corresponding to the first silicon nitride sidewall covering a first polysilicon layer on the wafer's back surface; step 3: growing a second silicon nitride layer on the wafer's front surface; step 4: etching the silicon nitride after stress transfer is completed, including: step 41: performing front single-wafer wet etching; step 42: performing batch wet etching to completely remove the second silicon nitride layer and reduces the thickness of the first silicon nitride layer on the back surface; step 5: completing the subsequent process. The application can improve the wafer flatness for improved photolithography for back-end-of-line processes and thereby increasing product yield.

## Claims

### Claim 1

A method of applying a stress memorization technique in making a semiconductor device, comprising a plurality of steps:
step 1: providing a semiconductor substrate, having a front surface and a back surface; forming a gate structure on the front surface, wherein the forming the gate structure on the front surface comprises:
performing thermal oxidation to the semiconductor substrate to simultaneously form a first oxide layer on the front surface and the back surface of the semiconductor substrate; simultaneously forming a first polysilicon layer on a surface of the first oxide layer on the front surface and the back surface of the semiconductor substrate;
performing a photolithography process to define an area of the gate structure, and sequentially etching the first oxide layer and the first polysilicon layer on the front surface of the semiconductor substrate to form the gate structure by superimposing a gate oxide layer and a polysilicon gate, wherein the gate oxide layer includes the first oxide layer after etching, and wherein the polysilicon gate includes the first polysilicon layer after etching;
step 2: forming sidewalls on a side surface of the gate structure, wherein the sidewalls comprises a first silicon nitride sidewall, wherein a process of forming the first silicon nitride sidewall comprises:
growing a first silicon nitride layer on each of the front surface and the back surface of the semiconductor substrate simultaneously, wherein the first silicon nitride layer on the front surface of the semiconductor substrate is formed to cover a top surface, the side surface of the gate structure and a surface outside the gate structure, and wherein the first silicon nitride layer on the back surface of the semiconductor substrate is formed to cover a surface of the first polysilicon layer;
performing comprehensive dry etching to the first silicon nitride layer on the front surface of the semiconductor substrate, wherein the first silicon nitride layer on the front surface of the semiconductor substrate is disposed on the side surface of the gate structure and dry-etched into a first silicon nitride sidewall, wherein the first silicon nitride layer on the back surface of the semiconductor substrate is not etched;
step 3: growing a second silicon nitride layer with stress for applying the stress memorization technique on the front surface of the semiconductor substrate;
step 4: performing a etching process to remove the silicon nitride layer after stress transfer is completed, wherein the stress transfer comprises steps of:
step 41: performing a first-time wet etching, wherein the first-time wet etching is a single-wafer wet etching for etching the second silicon nitride layer on the front surface of the semiconductor substrate;
step 42: performing a second-time wet etching, wherein the second-time wet etching is a batch wet etching, wherein the second-time wet etching simultaneously removes the second silicon nitride layer left on the front surface of the semiconductor substrate and reduces a thickness of the first silicon nitride layer on the back surface;
step 5: after step 4, performing subsequent back-end-of-line process of the semiconductor device, wherein the back-end-of-line process comprises a plurality of photolithography processes each follows after a cleaning process, wherein the first silicon nitride layer remaining on the back surface of the semiconductor substrate protects the first polysilicon layer on the back surface of the semiconductor substrate from being damaged in the cleaning process so as to have a uniformly flat back surface.

### Claim 2 (depends on 1)

The method of applying the stress memorization technique in making the semiconductor device according to claim 1, wherein the semiconductor substrate comprises a silicon substrate.

### Claim 3 (depends on 1)

The method of applying the stress memorization technique in making the semiconductor device according to claim 1, wherein the first polysilicon layer is grown by a thermal process in a furnace.

### Claim 4 (depends on 1)

The method of applying the stress memorization technique in making the semiconductor device according to claim 1, wherein in step 2, the sidewalls comprise double sidewalls;
after the first sidewall is made, performing light doping implantation to form a lightly doped drain region on the two sides of the corresponding gate structure of the semiconductor device;
forming a second sidewall, wherein the second sidewall comprises a first silicon oxide sidewall and the first silicon nitride sidewall; wherein the first silicon oxide sidewall covers a side surface of the first sidewall, and the first silicon nitride sidewall covers a side surface of the first silicon oxide sidewall.

### Claim 5 (depends on 4)

The method of applying the stress memorization technique in making the semiconductor device according to claim 4, wherein after the first silicon nitride sidewall is disposed and before the second silicon nitride layer is grown, the method further comprises performing amorphous implantation to enable a surface structure on the two sides of the gate structure of the semiconductor substrate to be amorphized.

### Claim 6 (depends on 1)

The method of applying the stress memorization technique in making the semiconductor device according to claim 1, wherein in step 4, the stress transfer is achieved by an annealing process.

### Claim 7 (depends on 6)

The method of applying the stress memorization technique in making the semiconductor device according to claim 6, wherein the annealing process comprises a rapid thermal annealing.

### Claim 8 (depends on 1)

The method of applying the stress memorization technique in making the semiconductor device according to claim 1, wherein the semiconductor device comprises an NMOS device and a PMOS device, and wherein in step 4, the stress transfer is performed for forming the NMOS device only.

### Claim 9 (depends on 8)

The method of applying the stress memorization technique in making the semiconductor device according to claim 8, wherein in step 3, the method further comprises forming a second oxide layer before forming the second silicon nitride layer.

### Claim 10 (depends on 1)

The method of applying the stress memorization technique in making the semiconductor device according to claim 1, wherein the method further comprises the following steps before the subsequent back-end-of-line process of step 5:
performing source and drain implantation to form a source region and the drain region of the semiconductor device in a self-aligned manner on the two sides of the gate structure;
forming self-aligned silicide on surfaces of the source region and the drain region; and
forming and planarizing a bottom interlayer film.

### Claim 11 (depends on 10)

The method of applying the stress memorization technique in making the semiconductor device according to claim 10, wherein after forming the bottom interlayer film, the method further comprises performing a gate structure replacement process, wherein the gate structure replacement process removes and replaces the polysilicon gate with a metal gate.

### Claim 12 (depends on 10)

The method of applying the stress memorization technique in making the semiconductor device according to claim 10, wherein the back-end-of-line process comprises:
forming a plurality of interlayer films, a plurality of front metal layers, a contact hole and a via hole, wherein the first of the plurality of front metal layers is in contact with one of the source region, the drain region and the metal gate at the bottom through the contact, wherein the plurality of front metal layers other than the first front metal layer is connected through the via hole; and
wherein the patterned structures of the contact hole, the via hole and the plurality of front metal layers are defined through photolithography processes.

### Claim 13 (depends on 1)

The method of applying the stress memorization technique in making the semiconductor device according to claim 1, wherein in step 2, the first silicon nitride layer is formed by a thermal process in a furnace.

### Claim 14 (depends on 1)

The method of applying the stress memorization technique in making the semiconductor device according to claim 1, wherein in step 3, the second silicon nitride layer is formed by a chemical vapor deposition process.

### Claim 15 (depends on 1)

The method of applying the stress memorization technique in making the semiconductor device according to claim 1, wherein a thickness of the first silicon nitride layer is in the range of 200 Å-220 Å; a thickness of the second silicon nitride layer is in a range of 200 Å-280 Å; after the second-time wet etching in step 42 is completed, a thickness of the first silicon nitride layer remaining on the back surface of the semiconductor substrate is in a range of 100 Å-180 Å.

### Claim 16 (depends on 15)

The method for making the semiconductor device by adopting the stress memorization technique according to claim 15, wherein etching solution for the first-time wet etching in step 41 is a hot phosphoric acid solution, a temperature is in a range of 140° C.-160° C., and a duration is in a range of 200 s-300 s.

### Claim 17 (depends on 15)

The method of applying the stress memorization technique in making the semiconductor device according to claim 15, wherein etching solution for the second-time wet etching in step 42 is a hot phosphoric acid solution, wherein a temperature is in a range of 140° C.-170° C., and a duration is in a range of 60 s-100 s.

### Claim 18 (depends on 1)

The method of applying the stress memorization technique in making the semiconductor device according to claim 1, wherein a technology node of the semiconductor device is 28 nm or less.