# US 11,443,983 B2 · Void-free high aspect ratio metal alloy interconnects and method of manufacture using a solvent-based etchant

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- Number: US 11,443,983 B2
- Document ID: US11443983B2
- Status: Granted
- Kind: B2
- Application number: 16/139,241
- Filed: 2018-09-24
- Published: 2020-03-26
- Granted: 2022-09-13
- Earliest claimed: 2018-09-24
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Shaestagir Chowdhury; Sirikarn Surawanvijit; Biswadeep Saha; Erica J. Thompson
- Web page: https://patentgrep.com/patent/US11443983B2

## CPC

- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- C22C 19/03: based on nickel
- C22C 19/07: based on cobalt
- H10P 50/667: {by liquid etching only}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/4437: {the principal metal being a transition metal}
- H10W 20/4446: {Refractory-metal alloys}
- C09K 13/00: Etching, surface-brightening or pickling compositions (for glass C03C15/00, {C03C25/66; for mortars, concrete, artificial or natural stone or ceramics C04B41/5338}; for metallic material C23F, C23G1/00, C25F1/00; {for semi-conductors H10P52/40})
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- C22C: ALLOYS (treatment of alloys C21D, C22F)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- C09K: MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE

## Abstract

An integrated circuit structure comprises a dielectric layer on a substrate. An open structure is in the dielectric layer, and a void-free metal-alloy interconnect is formed in the open structure, wherein the void-free metal-alloy interconnect comprise a metal-alloy comprising a combination of two or more metallic elements excluding any mixing effects of a seed layer or liner deposited in the open structure prior to a metal fill material, and excluding effects of any doping material on the metal fill material.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a dielectric layer on a substrate;
an open structure in the dielectric layer, the open structure having an aspect ratio of at least 5-1;
a void-free metal-alloy interconnect formed in the open structure, wherein the void-free metal-alloy interconnect comprise a metal-alloy comprising a combination of two or more metallic elements excluding any mixing effects of a seed layer or liner deposited in the open structure prior to a metal fill material, and excluding effects of any doping material on the metal fill material.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein the metal-alloy comprises 50-90% of a base metal and 10-50% of a second metal element.

### Claim 3 (depends on 1)

The integrated circuit structure of claim 1, wherein the metal-alloy is selected from a group comprising nickel-cobalt, nickel-tungsten, cobalt-tungsten, and nickel-cobalt-tungsten.

### Claim 4 (depends on 1)

The integrated circuit structure of claim 1, wherein the metal-alloy is selected from a group comprising nickel, cobalt, tungsten, ruthenium, molybdenum, vanadium, chromium.

### Claim 5 (depends on 1)

The integrated circuit structure of claim 1, wherein the open structure comprises one of a trench and a via.

### Claim 6 (depends on 5)

The integrated circuit structure of claim 5, wherein the trench and has an aspect ratio of 5-1 to 7-1.

### Claim 7 (depends on 5)

The integrated circuit structure of claim 5, wherein the via and has an aspect ratio of 12-1 to 20-1 and an opening having a critical dimension less than 50 nm.