# US 11,443,982 B2 · Formation of trench silicide source or drain contacts without gate damage

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,443,982 B2
- Document ID: US11443982B2
- Status: Granted
- Kind: B2
- Application number: 16/183,785
- Filed: 2018-11-08
- Published: 2020-05-14
- Granted: 2022-09-13
- Earliest claimed: 2018-11-08
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Andrew Greene; Ruilong Xie; Laertis Economikos; Veeraraghavan S. Basker; Chanro Park; Hui Zang
- Web page: https://patentgrep.com/patent/US11443982B2

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/0696: {by using sacrificial placeholders, e.g. using sacrificial plugs}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes one or more fins extending from a substrate, the one or more fins having source/drain epitaxial grown material (S/D epitaxy) thereon that merges one or more fins, a gate formed over the one or more fins, the gate including high k metal gate disposed between gate spacers and a metal liner over the S/D epitaxy and sides of the gate spacers. The gate includes a self-aligned contact cap over the HKMG and the metal liner.

## Claims

### Claim 1

A method of fabricating a semiconductor device, the method comprising:
receiving a structure that includes a fin extending from a substrate and covered by a dummy gate, the dummy gate including a sacrificial gate material covered by a hardmask material and having sides covered by a gate spacer, the fin including an exposed region not covered by the dummy gate and having an epitaxially grown material (S/D epitaxy) thereon;
forming an etch stop liner over the dummy gate and the S/D epitaxy formed of a first material;
forming an etch stop layer of a second material that is different than the first material over the etch stop liner;
forming an interlayer dielectric layer (ILD) over the etch stop layer;
removing the hardmask material to expose the sacrificial gate material;
partially removing the gate spacer and the sacrificial gate material to a level below a top of the ILD layer;
removing the sacrificial gate material to form a gate recess within the gate spacer;
forming a high-k metal gate (HKMG) in the gate trench by depositing a high-k dielectric layer and forming a metal gate over the high-k dielectric layer;
removing the ILD layer to expose the etch stop layer, wherein the etch stop layer, the HKMG and the etch stop liner protect the gate spacer from being removed during removal of the ILD;
removing the etch stop layer, wherein the etch stop liner and the HKMG protect the gate spacer from being removed during removal of the etch stop layer;
removing exposed portions of the etch stop liner;
depositing a metal liner over the S/D epitaxy and the HKMG;
depositing an organic planarization layer (OPL) over the S/D epitaxy and the HKMG and etching the OPL to expose the metal liner over the HKMG;
removing portions of the OPL to form a contact metal liner cut pattern opening through the OPL that exposes the metal liner over the ILD next to the fin;
etching the metal liner to expose the ILD next to the fin and to expose the HKMG;
filling the contact metal liner cut pattern opening with a source drain contact spacer and forming a self-aligned contact (SAC) cap over the HKMG;
removing exposed OPL; and
forming metal S/D contacts over the fin.

### Claim 2 (depends on 1)

The method of claim 1, wherein the etch stop liner is formed of hafnium dioxide (HfO2) or silicon dioxide (SiO2).

### Claim 3 (depends on 2)

The method of claim 2, wherein the etch stop layer is formed of silicon nitride (SiN).

### Claim 4 (depends on 1)

The method of claim 1, wherein after removing the hardmask the sacrificial gate material has a height that is about the same as that of the gate spacer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the sacrificial gate material is removed by a hot ammonia etch, by tetramethylammonium hydroxide etch or by a reactive chemical etch.

### Claim 6 (depends on 1)

The method of claim 1, wherein the high-k dielectric layer is formed of hafnium dioxide (HfO2).

### Claim 7 (depends on 6)

The method of claim 6, wherein the metal gate contact is formed of tungsten.

### Claim 8 (depends on 6)

The method of claim 6, wherein a work function metal is disposed between the metal gate contact and the high-k dielectric layer.

### Claim 9 (depends on 1)

The method of claim 1, wherein the SAC covers the gate spacer and the metal liner.

### Claim 10 (depends on 1)

The method of claim 1, wherein the high-k dielectric layer is formed of hafnium dioxide (HfO2).

### Claim 11

A method of fabricating at least two multi-fin finFETs, the method comprising:
receiving a structure that includes a plurality of fins extending from a substrate and covered by a dummy gate, the fins including a first group of fins separated from a second group of fins, the fins including an exposed region not covered by the dummy gate and having an epitaxially grown material (S/D epitaxy) thereon, the dummy gate including a sacrificial gate material covered by a hardmask material and having sides covered by a gate spacer;
forming an etch stop liner over the dummy gate and the S/D epitaxy formed of a first material;
forming an etch stop layer of a second material that is different than the first material over the etch stop liner;
forming an interlayer dielectric layer (ILD) over the etch stop layer;
removing the hardmask material to expose the sacrificial gate material;
partially removing the gate spacer and the sacrificial gate material to a level below a top of the ILD layer;
removing the sacrificial gate material to form a gate recess within the gate spacer;
forming a high-k metal gate (HKMG) in the gate trench by depositing a high-k dielectric layer and forming a metal gate over the high-k dielectric layer;
removing the ILD layer to expose the etch stop layer, wherein the etch stop layer, the HKMG and the etch stop liner protect the gate spacer from being removed during removal of the ILD;
removing the etch stop layer, wherein the etch stop liner and the HKMG protect the gate spacer from being removed during removal of the etch stop layer;
removing exposed portions of the etch stop liner;
depositing a metal liner over the S/D epitaxy and the HKMG;
depositing an organic planarization layer (OPL) over the S/D epitaxy and the HKMG and etching the OPL to expose the metal liner over the HKMG;
removing portions of the OPL to form a contact metal liner cut pattern opening through the OPL that exposes the metal liner over the ILD next to the fin;
etching the metal liner to expose the ILD next to the fin and to expose the HKMG;
filling the contact metal liner cut pattern opening with a source drain contact spacer and forming a self-aligned contact (SAC) cap over the HKMG;
removing exposed OPL; and
forming metal S/D contacts over the fin.

### Claim 12 (depends on 11)

The method of claim 11, wherein the etch stop liner is formed of hafnium dioxide (HfO2) or silicon dioxide (SiO2).

### Claim 13 (depends on 12)

The method of claim 12, wherein the etch stop layer is formed of silicon nitride (SiN).

### Claim 14 (depends on 11)

The method of claim 11, wherein after the hardmask is removed the sacrificial gate material has a height that is about the same as that of the gate spacer.

### Claim 15 (depends on 11)

The method of claim 11, wherein the sacrificial gate material is removed by a hot ammonia etch, by a tetramethylammonium hydroxide etch or by a reactive chemical etch.

### Claim 16 (depends on 11)

The method of claim 11, wherein the metal gate contact is formed of tungsten and a work function metal is disposed between the metal gate contact and the high-k dielectric layer.

### Claim 17 (depends on 11)

The method of claim 11, wherein the SAC cap covers the gate spacer and the metal liner.