# US 11,443,979 B2 · Semiconductor device

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- Number: US 11,443,979 B2
- Document ID: US11443979B2
- Status: Granted
- Kind: B2
- Application number: 16/836,930
- Filed: 2020-04-01
- Published: 2021-10-07
- Granted: 2022-09-13
- Earliest claimed: 2020-04-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsin-Yi Lee; Cheng-Lung Hung; Da-Yuan Lee
- Web page: https://patentgrep.com/patent/US11443979B2

## CPC

- H10W 20/081: {by forming openings in the dielectric parts}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/364: {of IGFETs}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/664: {the additional layers comprising a barrier layer between the layer of silicon and an upper metal or metal silicide layer}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10P 76/2041: {Photolithographic processes}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device may include a substrate, a first transistor disposed on the substrate, and a second transistor disposed on the substrate. The first transistor includes a first gate structure. The first gate structure of the first transistor may include a first high-k layer, a first work function layer, an overlying work function layer, and a first capping layer sequentially disposed on the substrate. The second transistor includes a second gate structure. The second gate structure comprises a second gate structure, the second gate structure comprising a second high-k layer, a second work function layer, and a second capping layer sequentially disposed on the substrate. The first capping layer and the second capping layer comprise a material having higher resistant to oxygen or fluorine than materials of the second work function layer and the overlying work function layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a first transistor disposed on the substrate, and comprising a first gate structure, wherein the first gate structure comprises a first high-k layer, a first work function layer, a overlying work function layer, and a first capping layer sequentially disposed on the substrate; and
a second transistor disposed on the substrate, and comprising a second gate structure, the second gate structure comprising a second high-k layer, a second work function layer, and a second capping layer sequentially disposed on the substrate,
wherein the material of the first capping layer and the second capping layer comprise a material having higher resistant to oxygen or fluorine than materials of the second work function layer and the overlying work function layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a material of the second work function layer comprises aluminum element.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the material of the second work function layer comprises TiAl, TiAlC, TaAl, TaAlC, or a combination thereof.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein the first capping layer and the second capping layer comprise aluminum element.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the first capping layer and the second capping layer comprise a metal nitride, and the metal nitride comprises a nitride of aluminum and a nitride of tungsten.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein materials of the first capping layer and the second capping layer comprises aluminum nitride (AlxNy), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaALN), tungsten aluminum nitride (WAlN), tungsten nitride (WN) or a combination thereof, where ‘x’ is equal to about 1 to 3; and ‘y’ is equal to about 1 to 3.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first transistor further comprises an overlying work function layer disposed between the first work function layer and the first capping layer, and a material of the overlying work function layer is the same as the material of the second work function layer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the overlying work function layer is in direct contact with the first capping layer, and the second work function layer is in direct contact with the second capping layer.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the first transistor further comprises a first glue layer and a first gate fill layer on the first capping layer, and a second glue layer and a second gate fill layer on the second capping layer.

### Claim 10

A semiconductor device, comprising:
a substrate;
a first transistor disposed on the substrate, and comprising a first gate structure, wherein the first gate structure comprises a first high-k layer, a first work function layer, and a first capping layer sequentially disposed on the substrate; and
a second transistor disposed on the substrate, and comprising a second gate structure, wherein the second gate structure comprises a second high-k layer, a second work function layer, and a second capping layer sequentially disposed on the substrate,
wherein a material of the second work function layer comprises Ta element and Al element,
wherein the material of the first capping layer and the second capping layer comprise a material having higher resistant to oxygen or fluorine than materials of the second work function layer.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the first work function layer comprises a first layer, and the second work function layer comprises the first layer and a second layer on the first layer, and the first layer comprises a TiN layer or a TaN layer, and the second layer comprises a TaAlC layer.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, further comprising:
a third transistor disposed on the substrate, and comprising a third gate structure, wherein the third gate structure comprises a third high-k layer and a third work function layer sequentially disposed on the substrate,
wherein a material of the third work function layer comprises Ti element and Al element.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the material of the third work function layer comprises the first layer and a third layer on the first layer, and the third layer comprises TiAlC.

### Claim 14

A semiconductor device, comprising:
a substrate;
a plurality of semiconductor nanosheets disposed over the substrate; and
a gate stack wrapping each of the plurality of semiconductor nanosheets, wherein the gate stack comprises:
a gate dielectric layer wrapping each of the plurality of semiconductor nanosheets;
a work function layer surrounding the gate dielectric layer;
a gate fill material surrounding the work function layer; and
a barrier layer between the work function layer and the gate fill material, wherein the barrier layer is located in an inner sheet region between two adjacent semiconductor nanosheets and in an outer sheet region other than the inner sheet region.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the work function layer comprises a first part and a second part surrounding the two adjacent semiconductor nanosheets, and the first part and the second part are not merged in the inner sheet region.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the first part and the second part are separated by the barrier layer.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, wherein the work function layer comprises TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, TiAlC, or a combination thereof.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, wherein the barrier layer comprises a nitride of metal.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the nitride of metal comprises TiN, TaN, Si-doped TiN (TSN), or a combination thereof.

### Claim 20 (depends on 14)

The semiconductor device of claim 14, further comprising:
a glue layer between the barrier layer and the gate fill layer.