# US 11,443,971 B2 · 3D semiconductor device and structure with memory

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- Number: US 11,443,971 B2
- Document ID: US11443971B2
- Status: Granted
- Kind: B2
- Application number: 17/146,416
- Filed: 2021-01-11
- Published: 2021-05-06
- Granted: 2022-09-13
- Earliest claimed: 2010-11-18
- Assignees: Monolithic 3D Inc.
- Applicants: Monolithic 3D Inc.
- Inventors: Zvi Or-Bach; Brian Cronquist; Deepak C. Sekar
- Web page: https://patentgrep.com/patent/US11443971B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 8/16: Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
- H10B 10/00: Static random access memory [SRAM] devices
- H10B 10/125: {the MOSFET being a thin film transistor [TFT]}
- H10B 10/18: {Peripheral circuit regions}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- H10B 12/50: {Peripheral circuit region structures}
- H10B 20/00: Read-only memory [ROM] devices
- H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 41/40: characterised by the peripheral circuit region
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/40: characterised by the peripheral circuit region
- H10D 10/051: {of vertical BJTs (of heterojunction BJTs H10D10/021; of Schottky BJTs H10D10/031; of thin film BJTs H10D10/041)}
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/0512: {of FETs having PN homojunction gates}
- H10D 30/503: {having non-rectangular cross-sections}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/711: {having floating bodies}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/027: {by etching at gate locations}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/837: {comprising vertical IGFETs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/907: {CMOS gate arrays}
- H10D 84/998: {Input and output buffer/driver structures}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10D 89/10: Integrated device layouts
- H10P 90/1916: {with separation or delamination along an ion implanted layer, e.g. Smart-cut}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/491: {Antifuses, i.e. interconnections changeable from non-conductive to conductive}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10B 10/12: {comprising a MOSFET load element}
- H10B 12/05: {Making the transistor}
- H10B 12/482: {Bit lines}
- H10D 30/0193: {by modifying properties of the stacked channels}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 86/0214: {using temporary substrates}
- H10D 86/40: characterised by multiple TFTs
- H10D 86/60: wherein the TFTs are in active matrices
- H10P 72/7426: {used as a support during build up manufacturing of active devices}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7434: {used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate}
- H10W 40/10: Arrangements for heating
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 46/101: {characterised by the type of information, e.g. logos or symbols}
- H10W 46/301: {for alignment}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07331: {Connecting techniques}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors and a first metal layer, where the first transistors include forming memory control circuits; a second level including a plurality of second transistors; a third level including a plurality of third transistors, where the second level is above the first level, and where the third level is above the second level; a second metal layer above the third level; and a third metal layer above the second metal layer, where the second transistors are aligned to the first transistors with less than 140 nm alignment error, where the second level includes a plurality of first memory cells, where the third level includes a plurality of second memory cells, and where the memory control circuits are designed to adjust a memory write voltage according to the device specific process parameters.

## Claims

### Claim 1

A 3D semiconductor device, the device comprising:
a first level comprising a plurality of first single: crystal transistors;
a plurality of memory control circuits formed from at least a portion of said plurality of first single-crystal transistors;
a first metal layer disposed atop said plurality of first single-crystal transistors;
a second level comprising a plurality of second transistors;
a third level comprising a plurality of third transistors;
wherein said second level is above said first level, and
wherein said third level is above said second level;
a second metal layer above said third level; and
a third metal layer above said second metal layer,
wherein said plurality of second transistors are aligned to said plurality of first single crystal transistors with less than 140 nm and greater than about 2 nm of alignment error;
wherein said third metal comprises bit lines,
wherein said second level comprises a plurality of first memory cells,
wherein said third level comprises a plurality of second memory cells,
wherein one of said plurality of second transistors is at least partially self-aligned to at least one of said plurality of third transistors, being processed following a same lithography step,
wherein each of said plurality of second memory cells comprises at least one of said plurality of third transistors,
wherein at least one of said plurality of second transistors is disposed at least partially atop at least a portion of said memory control circuits, and
wherein at least one of said memory control circuits controls operation of at least one of said plurality of first memory cells.

### Claim 2 (depends on 1)

The 3D semiconductor device according to claim 1, further comprising:
a connective path between said plurality of second transistors and said plurality of first single crystal transistors,
wherein said path comprises a through-layer via (TLV), and
wherein said through-layer via has a diameter less than 400 nm.

### Claim 3 (depends on 1)

The 3D semiconductor device according to claim 1,
wherein fabrication processing of said device comprises first processing said first single crystal transistors followed by processing said second transistors and then processing said third transistors, and
wherein said first processing said first transistors accounts for a temperature and time associated with processing said second transistors and said third transistors by adjusting a process thermal budget of said first transistors accordingly.

### Claim 4 (depends on 1)

The 3D semiconductor device according to claim 1,
wherein a memory array comprises a portion of or all of said plurality of first memory cells,
wherein a memory location or plurality of memory locations within said memory array comprise device specific process parameter data, and
wherein said memory array comprises FB-RAM cells.

### Claim 5 (depends on 1)

The 3D semiconductor device according to claim 1, further comprising:
an upper level above said third metal layer,
wherein said upper level comprises a mono-crystalline silicon layer.

### Claim 6 (depends on 1)

The 3D semiconductor device according to claim 1, further comprising:
a first set of external connections beneath said first level to connect said device to a first external device,
wherein said first set of external connections comprises through vias.

### Claim 7 (depends on 1)

The 3D semiconductor device according to claim 1,
wherein at least one of said plurality of second transistors is above at least a portion of said first metal layer.

### Claim 8 (depends on 1)

The 3D semiconductor device according to claim 1,
wherein said memory control circuits control a magnitude, duration, and repetition rate of memory write voltages delivered to said plurality of first memory cells and to said plurality of second memory cells by using a distance between a write driver circuit and an associated memory cell.

### Claim 9 (depends on 1)

The 3D semiconductor device according to claim 1,
wherein said memory control circuits control a magnitude, duration, and repetition rate of memory write voltages by using one or more temperatures at which said 3D semiconductor device is operating.

### Claim 10

A 3D semiconductor device, the device comprising:
a first level comprising both a plurality of first single-crystal transistors and a first metal layer, said first metal layer disposed atop said plurality of first single-crystal transistors;
a plurality of memory control circuits formed from at least a portion of said plurality of first single-crystal transistors;
a second level comprising a plurality of second transistors;
a third level comprising a plurality of third transistors;
wherein said second level is above said first level, and
wherein said third level is above said second level;
a second metal layer above said third level;
a third metal layer above said second metal layer;
wherein said second transistors are aligned to said first transistors with less than 140 nm and greater than about 2 nm of alignment error,
wherein said third metal comprises bit lines,
wherein said second level comprises a plurality of first memory cells,
wherein said third level comprises a plurality of second memory cells,
wherein one of said plurality of second transistors is at least partially self-aligned to at least one of said plurality of third transistors being processed following a same lithography step,
wherein at least one of said plurality of second transistors is disposed at least partially atop at least a portion of said memory control circuits,
wherein each of said plurality of second memory cells comprises at least one of said plurality of third transistors; and
an upper level disposed above said third metal layer;
wherein said upper level comprises a mono-crystalline silicon layer.

### Claim 11 (depends on 10)

The 3D semiconductor device according to claim 10, further comprising:
a connective path between said plurality of second transistors and said plurality of first single: crystal transistors;
wherein said path comprises a through-layer via (TLV), and
wherein said TLV has a diameter less than 400 nm.

### Claim 12 (depends on 10)

The 3D semiconductor device according to claim 10,
wherein at least one of said plurality of second transistors comprises polysilicon.

### Claim 13 (depends on 10)

The 3D semiconductor device according to claim 10,
wherein a memory array comprises a portion of or all of said plurality of first memory cells,
wherein a memory location, or plurality of memory locations, within said memory array comprise device-specific process parameter data, and
wherein said memory array comprises FB-RAM cells.

### Claim 14 (depends on 10)

The 3D semiconductor device according to claim 10, further comprising:
at least one TSV (Through Silicon Via) through said mono-crystalline layer to provide connections to an external device.

### Claim 15 (depends on 10)

The 3D semiconductor device according to claim 10,
wherein at least one of said plurality of second transistors is at least partially above at least one of said plurality of first single-crystal transistors.

### Claim 16 (depends on 10)

The 3D semiconductor device according to claim 10, further comprising:
a first set of external connections disposed beneath said first level that connects said device to a first external device; and
a second set of external connections disposed atop said second metal layer that connects said device to a second external device.

### Claim 17

A 3D semiconductor device, the device comprising:
a first level comprising both a plurality of first single: crystal transistors and a first metal layer;
a plurality of memory control circuits formed from at least a portion of said plurality of first single-crystal transistors;
wherein said first metal layer is disposed atop said plurality of first single-crystal transistors;
a second level comprising a plurality of second transistors;
a third level comprising a plurality of third transistors;
wherein said second level is above said first level, and
wherein said third level is above said second level;
a second metal layer above said third level; and
a third metal layer above said second metal layer,
wherein said second transistors are aligned to said first transistors with less than 140 nm and greater than about 2 nm of alignment error,
wherein said second level comprises a plurality of first memory cells,
wherein said third level comprises a plurality of second memory cells,
wherein said memory control circuits control a magnitude and a duration of memory write voltages delivered to said plurality of first memory cells and to said plurality of second memory cells by using a distance between a write driver circuit and an associated memory cell, and
wherein said memory control circuits additionally control memory write voltages by using one or more temperatures at which said 3D semiconductor device is operating, as determined by monitoring charge loss rates in one or more reference cells; whereon said one or more temperatures are determined by using one or more reference cells and by monitoring charge loss rates in said reference cells.

### Claim 18 (depends on 17)

The 3D semiconductor device according to claim 17, further comprising at least one TSV (Through Silicon Via) through at least a part of said first level to provide connections to an external device.

### Claim 19 (depends on 17)

The 3D semiconductor device according to claim 17,
wherein at least one of said plurality of third transistors is a junction-less transistor;
wherein each of said junction-less transistors (JLT) comprise a JLT channel, a JLT drain, and a JLT source, and
wherein said JLT channel, said JLT drain, and said JLT source comprise a same dopant type.

### Claim 20 (depends on 17)

The 3D semiconductor device according to claim 17,
wherein one of said plurality of second transistors is at least partially self-aligned to at least one of said plurality of third transistors being processed following a same lithography step.

### Claim 21 (depends on 17)

The 3D semiconductor device according to claim 17, further comprising:
an upper level above said third metal layer;
wherein said upper level comprises a mono-crystalline silicon layer.

### Claim 22 (depends on 17)

The 3D semiconductor device according to claim 17, further comprising:
a connective path between said plurality of second transistors and said plurality of first single: crystal transistors,
wherein said path comprises a through-layer via (TLV), and
wherein said TLV has a diameter less than 400 nm.