# US 11,443,958 B2 · Semiconductor device and corresponding method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,958 B2 - Document ID: US11443958B2 - Status: Granted - Kind: B2 - Application number: 17/108,471 - Filed: 2020-12-01 - Published: 2021-06-03 - Granted: 2022-09-13 - Earliest claimed: 2019-12-02 - Assignees: STMicroelectronics S.r.l.; STMicroelectronics (Malta) Ltd - Applicants: STMicroelectronics S.r.l.; STMicroelectronics (Malta) Ltd - Inventors: Roseanne Duca; Dario Paci; Pierpaolo Recanatini - Web page: https://patentgrep.com/patent/US11443958B2 ## CPC - H10P 95/90: Thermal treatments, e.g. annealing or sintering - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/40: Leadframes - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70) - H10W 72/926: {Multiple bond pads having different sizes} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A leadframe includes a die pad and a set of electrically conductive leads. A semiconductor die, having a front surface and a back surface opposed to the front surface, is arranged on the die pad with the front surface facing away from the die pad. The semiconductor die is electrically coupled to the electrically conductive leads. A package molding material is molded over the semiconductor die arranged on the die pad. A stress absorbing material contained within a cavity delimited by a peripheral wall on the front surface of the semiconductor die is positioned intermediate at least one selected portion of the front surface of the semiconductor die and the package molding material. ## Claims ### Claim 1 A semiconductor device, comprising: a leadframe comprising a die pad and a set of electrically conductive leads; a semiconductor die having a first surface and a second surface opposed to the first surface, the semiconductor die being arranged on the die pad with said first surface facing away from the die pad; an electrical coupling between the semiconductor die and said electrically conductive leads; a containment structure on the first surface of the semiconductor die, said containment structure comprising a peripheral wall configured to define a closed perimeter around a portion of said first surface of the semiconductor die; stress absorbing material on the first surface of the semiconductor die and contained by the containment structure within said closed perimeter; and package molding material molded over the semiconductor die, the containment structure and the stress absorbing material. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the peripheral wall of said containment structure is made of a resin material and wherein said stress absorbing material comprises a material selected from a group consisting of a silicone material and a soft gel material. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein said containment structure comprises a resin material. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein a height of said containment structure is equal to or higher than 100 μm. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein said stress absorbing material comprises a material selected from a group consisting of a silicone material and a soft gel material. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the stress absorbing material has an elastic modulus lower than 2 MPa. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the stress absorbing material has an elastic modulus lower than 1 MPa. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the semiconductor die comprises electrically conductive bonding pads located at said first surface and outside of said containment structure. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein the semiconductor die comprises a region sensitive to piezoresistive effect located within the selected portion of the first surface of the semiconductor die. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein the semiconductor die comprises a sensor device located within the selected portion of the first surface of the semiconductor die. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein the sensor device is a Hall sensor device. ### Claim 12 (depends on 1) The semiconductor device of claim 1, wherein the semiconductor die comprises electrically conductive bonding pads located at said first surface and outside of said containment structure. ### Claim 13 A semiconductor device, comprising: a semiconductor die having a first surface and a second surface opposed to the first surface; a containment structure on the first surface of the semiconductor die, said containment structure comprising a peripheral wall configured to define a closed perimeter around a portion of said first surface of the semiconductor die; stress absorbing material on the first surface of the semiconductor die and contained by the containment structure within said closed perimeter; and package molding material molded over the semiconductor die, the containment structure and the stress absorbing material. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein the peripheral wall is made of a resin material and wherein said stress absorbing material comprises a material selected from a group consisting of a silicone material and a soft gel material. ### Claim 15 (depends on 13) The semiconductor device of claim 13, wherein said peripheral wall is made of a resin material. ### Claim 16 (depends on 13) The semiconductor device of claim 13, wherein said stress absorbing material comprises a material selected from a group consisting of a silicone material and a soft gel material. ### Claim 17 (depends on 13) The semiconductor device of claim 13, wherein the stress absorbing material has an elastic modulus lower than 2 MPa. ### Claim 18 (depends on 13) The semiconductor device of claim 13, wherein the stress absorbing material has an elastic modulus lower than 1 MPa. ### Claim 19 (depends on 13) The semiconductor device of claim 13, wherein said portion of said first surface is a piezoresistive sensor region. ### Claim 20 (depends on 13) The semiconductor device of claim 13, wherein said portion of said first surface is a sensor device. ### Claim 21 (depends on 20) The semiconductor device of claim 20, wherein the sensor device is a Hall sensor device.