# US 11,443,957 B2 · Metal oxide layered structure and methods of forming the same

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- Number: US 11,443,957 B2
- Document ID: US11443957B2
- Status: Granted
- Kind: B2
- Application number: 16/876,938
- Filed: 2020-05-18
- Published: 2020-09-03
- Granted: 2022-09-13
- Earliest claimed: 2015-02-13
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jing-Cheng Lin; Cheng-Lin Huang
- Web page: https://patentgrep.com/patent/US11443957B2

## CPC

- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/065: {by making at least a portion of the conductive part non-conductive, e.g. by oxidation}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/685: comprising multiple insulating layers
- H10W 70/69: Insulating materials thereof
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9413: {on encapsulations}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 Å. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.

## Claims

### Claim 1

A method comprising:
forming a metallic structure over a dielectric layer, the dielectric layer being located over an encapsulant encapsulating a semiconductor die; and
adding oxygen to a portion of the metallic structure until the portion of the metallic structure has a ratio of metal atoms to oxygen atoms that is substantially 1:1, a thickness of the portion being at least 50 Å.

### Claim 2 (depends on 1)

The method of claim 1, wherein the adding oxygen comprises forming a native oxide from the metallic structure.

### Claim 3 (depends on 2)

The method of claim 2, wherein the adding oxygen comprises exposing the portion of the metallic structure to an oxygen-containing plasma.

### Claim 4 (depends on 3)

The method of claim 3, further comprising forming a native oxide from at least part of the portion of the metallic structure.

### Claim 5 (depends on 1)

The method of claim 1, further comprising forming a native oxide from at least part of the portion of the metallic structure.

### Claim 6 (depends on 1)

The method of claim 1, wherein the adding oxygen comprises:
removing a native oxide; and
exposing the portion of the metallic structure to an oxygen-containing plasma.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
forming a native oxide from at least part of the portion of the metallic structure; and
forming a metallic oxide layer over the native oxide, the metallic oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1.

### Claim 8

A method comprising:
encapsulating a semiconductor die with an encapsulant;
forming a metallization pattern over the encapsulant; and
exposing the metallization pattern to an ambient to add oxygen to form a metal-oxide layer, the metal-oxide layer having a ratio of atoms of oxygen to atoms of a metal of substantially 1:1, the metal-oxide layer being at least 50 Å thick.

### Claim 9 (depends on 8)

The method of claim 8, further comprising removing a native oxide from the metallization pattern prior to the exposing the metallization pattern.

### Claim 10 (depends on 8)

The method of claim 8, wherein the exposing the metallization pattern to an ambient exposes the metallization pattern to an oxygen-containing plasma comprises an ozone plasma.

### Claim 11 (depends on 10)

The method of claim 10, wherein the oxygen-containing plasma further comprises nitrogen.

### Claim 12 (depends on 8)

The method of claim 8, further comprising forming a native oxide after the exposing the metallization pattern.

### Claim 13 (depends on 12)

The method of claim 12, further comprising exposing the native oxide to a second oxygen-containing plasma to form a second metal-oxide layer, the second metal-oxide layer having a second ratio of atoms of oxygen to atoms of a metal of substantially 1:1.

### Claim 14 (depends on 12)

The method of claim 12, further comprising forming a dielectric layer in physical contact with the native oxide.

### Claim 15 (depends on 8)

The method of claim 8, further comprising forming a native oxide prior to the exposing the metallization pattern.

### Claim 16

A method comprising:
encapsulating an integrated circuit die with an encapsulant;
forming a dielectric layer over the encapsulant and the integrated circuit die;
forming a metallization pattern over the dielectric layer; and
treating the metallization pattern to add oxygen, the treating forming a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1 over the metallization pattern, a thickness of the metal oxide layer being at least 50 Å.

### Claim 17 (depends on 16)

The method of claim 16, further comprising removing a native oxide from the metallization pattern before the treating the metallization pattern.

### Claim 18 (depends on 16)

The method of claim 16, wherein the treating the metallization pattern forms the metal oxide layer on a native oxide, the native oxide being disposed between the metallization pattern and the metal oxide layer.

### Claim 19 (depends on 16)

The method of claim 16, wherein the thickness is not more than 200 Å.

### Claim 20 (depends on 16)

The method of claim 16, wherein the thickness is not more than 100 Å.