# US 11,443,955 B2 · Semiconductor device and fabrication method thereof

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- Number: US 11,443,955 B2
- Document ID: US11443955B2
- Status: Granted
- Kind: B2
- Application number: 16/853,110
- Filed: 2020-04-20
- Published: 2020-10-22
- Granted: 2022-09-13
- Earliest claimed: 2019-04-22
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Jisong Jin
- Web page: https://patentgrep.com/patent/US11443955B2

## CPC

- H10P 50/73: {using masks for insulating materials}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/364: {of IGFETs}
- H10D 64/511: {for IGFETs}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10P 50/283: {by chemical means}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a to-be-etched layer having a plurality of first regions and second regions; forming a first mask layer on the to-be-etched layer; doping portions of the first mask layer outside the second trench regions; forming a second mask layer on the first mask layer; forming a first trench penetrating the first mask layer and the second mask layer over the first regions; forming a mask sidewall spacer on sidewall surfaces of the first trench; removing the second mask layer; and removing the first mask layer in the second trench regions using the mask sidewall spacers and the doped portions of the first mask layer as an etching mask to form seconds trenches over the second trench regions of the plurality of second regions. The sidewall surface of the second trench exposes a corresponding mask sidewall spacer.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
providing a to-be-etched layer, wherein the to-be-etched layer includes a plurality of first regions and a plurality of second regions that are alternately arranged along a first direction, a first region of the plurality of first regions adjoins a second region of the plurality of second regions, and the second region includes a second trench region;
forming a first mask layer on the plurality of first regions and the plurality of second regions of the to-be-etched layer;
doping portions of the first mask layer outside second trench regions of the plurality of second regions;
after doping the portions of the first mask layer, forming a second mask layer on the first mask layer;
forming a first trench penetrating the first mask layer and the second mask layer over a first region of the plurality of first regions;
forming a mask sidewall spacer on sidewall surfaces of the first trench;
after forming the mask sidewall spacer, removing the second mask layer; and
after removing the second mask layer removing the first mask layer over the second trench regions by an etching process using the mask sidewall spacer and the doped portions of the first mask layer as an etching mask to form second trenches over the plurality of second trench regions of the plurality of second regions, wherein a sidewall surface of the second trench exposes a corresponding mask sidewall spacer of an adjacent first trench.

### Claim 2 (depends on 1)

The method according to claim 1, wherein:
the doping ions include boron ions or arsenic ions.

### Claim 3 (depends on 1)

The method according to claim 1, wherein before doping the ions in the portions of the first mask layer outside the second trench regions,
the first mask layer is made of one or more of amorphous silicon, silicon nitride, or silicon oxide; and
the second mask layer is made of one or more of amorphous silicon, silicon nitride, or silicon oxide.

### Claim 4 (depends on 1)

The method according to claim 1, wherein:
a ratio between a thickness of the first mask layer and a thickness of the second mask layer is in a range of approximately 1:4 to 4:1.

### Claim 5 (depends on 1)

The method according to claim 1, wherein:
the first trenches are formed by an anisotropic dry etching process; and
when forming the first trenches, a ratio of etch rates between doped portions of the first mask layer and un-doped portions of the first mask layer is in a range of approximately 1:1.5 to 1.5:1.

### Claim 6 (depends on 1)

The method according to claim 1, wherein forming the mask sidewall spacer comprises:
forming a mask sidewall spacer film on sidewall surfaces and bottoms of the first trenches, and a top surface of the second mask layer; and
etching back the mask sidewall spacer film until portions of the mask sidewall spacer film on the bottoms of the first trenches and a portion of the mask sidewall spacer film on the top surface of the second mask layer are removed.

### Claim 7 (depends on 1)

The method according to claim 1, wherein:
a thickness of the mask sidewall spacer is in a range of approximately 5 nm-20 nm.

### Claim 8 (depends on 1)

The method according to claim 1, wherein:
along a direction perpendicular to a top surface of the to-be-etched layer, a height of the mask sidewall spacer is in a range of approximately 30 nm-80 nm.

### Claim 9 (depends on 1)

The method according to claim 1, wherein:
the mask sidewall spacer is made of one or more of SiO2, SiN, TiO2, TiN, AlN, or Al2O3.

### Claim 10 (depends on 1)

The method according to claim 1, wherein:
the portions of the first mask layer over the second trench regions are removed by a wet etching process.

### Claim 11 (depends on 1)

The method according to claim 1, wherein:
the portions of the first mask layer over the second trench regions and the second mask layer are made of a same material; and
the second mask layer and the portions of the first mask layer over the second trench regions are removed by a same etching process.

### Claim 12 (depends on 1)

The method according to claim 1, further comprising:
etching a portion of the to-be-etched layer at the bottom of the first trench to form a first targeted trench in the to-be-etched layer;
etching a portion of the to-be-etched layer at the bottom of the second trench to form a second targeted trench in the to-be-etched layer;
forming a first conductive layer in the first targeted trench; and
forming a second conductive layer in the second targeted trench.

### Claim 13 (depends on 1)

The method according to claim 1, before forming the first mask layer, further comprising:
forming a first adhesion layer on the to-be-etched layer;
forming a bottom hard mask layer on the first adhesion layer; and
forming a second adhesion layer on the bottom hard mask layer.

### Claim 14 (depends on 1)

The method according to claim 1, after forming the second trenches, further comprising:
etching a portion of the to-be-etched layer at a bottom of the first trench to form a first targeted trench;
etching a portion of the to-be-etched layer at a bottom of the second trench to form a second targeted trench;
forming a first conductive layer in the first targeted trench; and
forming a second conductive layer in the second targeted trench.