# US 11,443,937 B2 · Semiconductor ICF target processing

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- Number: US 11,443,937 B2
- Document ID: US11443937B2
- Status: Granted
- Kind: B2
- Application number: 15/930,056
- Filed: 2020-05-12
- Published: 2021-11-18
- Granted: 2022-09-13
- Earliest claimed: 2020-05-12
- Assignees: Innoven Energy LLC
- Applicants: Tyler A. Lowrey
- Inventors: Tyler A. Lowrey
- Web page: https://patentgrep.com/patent/US11443937B2

## CPC

- B81C 1/00103: {Structures having a predefined profile, e.g. sloped or rounded grooves}
- H10P 70/234: {the processing being the formation of vias or contact holes}
- B81C 1/00531: {Dry etching}
- B81C 1/00539: {Wet etching}
- B81C 99/0095: {Aspects relating to the manufacture of substrate-free structures, not covered by groups B81C99/008 - B81C99/009}
- G21B 1/19: Targets for producing thermonuclear fusion reactions, e.g. pellets for irradiation by laser or charged particle beams
- H10P 50/73: {using masks for insulating materials}
- H10P 70/15: {by wet cleaning only (H10P70/52 takes precedence)}
- H10P 90/00: Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- Y02E 30/10: Nuclear fusion reactors
- B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G21B: FUSION REACTORS (uncontrolled reactors G21J)
- Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION

## Abstract

A method of manufacturing a semiconductor ICF target is described. On an n-type silicon wafer a plurality of hard mask layers are etched to a desired via pattern. Then isotropically etching hemispherical cavities, lithographically patterning the hard mask layers, conformally depositing ablator/drive material(s) and shell layer material(s), inserting hollow silicon dioxide fuel spheres in the hemisphere cavities, thermally bonding a mating wafer with matching hemisphere cavities and etching in ethylene diamine-pryrocatechol-water mixture to selectively remove n-type silicon and liberate the spherical targets.

## Claims

### Claim 1

A process for manufacturing a plurality of individual spherical devices in parallel from a wafer of semiconductor material, comprising:
creating a first wafer by:
depositing one or more hard mask films upon a single-crystal n-type silicon substrate;
applying a uniform coat of photoresist pattern on top of the one or more hard mask films, wherein the first wafer is rotating as the uniform coat of photoresist pattern is applied;
etching through the one or more hard mask films with vias, wherein the vias range in diameter from 1 μm to 1 mm;
forming hemispherical cavities using an isotropic dry etch of the n-type silicon substrate having one or more hard mask films, wherein the hemispherical cavities range in diameter from 100 μm to 5 cm;
using a Chemical Mechanical Planarization (CMP) process to polish and remove one or more of the hard mask films;
incorporating a p-type dopant on a surface of the hemispherical cavities;
placing hollow silicon dioxide fuel spheres within the hemispherical cavity; and
filling the hollow silicon dioxide fuel spheres with a fusion fuel mixture,
creating a second wafer by repeating the above steps of creating a first wafer, wherein the second wafer has the same pattern of hemispherical cavities as the first wafer;
mating the first and second wafers together;
adhesively bonding the first and second wafers together;
etching to selectively remove what remains from the single-crystal n-type silicon substrate to liberate a spherical device; and
repeating all of the above steps that produce the plurality of individual spherical devices, in parallel.

### Claim 2 (depends on 1)

The process of claim 1, wherein said single-crystal n-type silicon substrate is customized to a thickness ranging from approximately 500 to 5 cm.

### Claim 3 (depends on 2)

The process of claim 2, wherein the plurality of hard mask films are composed of one or more of the following materials: silicon dioxide, silicon nitride and chromium.

### Claim 4 (depends on 3)

The process of claim 3, wherein the plurality of hard mask films are each customized to a thickness ranging from approximately 200 Å to 100,000 Å.

### Claim 5 (depends on 4)

The process of claim 4, further comprising:
isotropically etching the hemispherical cavities with a sulfur hexafluoride dry etch.

### Claim 6 (depends on 5)

The process of claim 5, further comprising:
using thermally diffuse boron atoms in the p-type doping of the surface of the hemispherical cavity.

### Claim 7 (depends on 6)

The process of claim 6, wherein the p-type doping of the surface of the hemispherical cavity is performed to a depth of approximately 1-200 μm for the thermally diffuse boron atoms.

### Claim 8 (depends on 7)

The process of claim 7, further comprising;
conformally depositing a shell layer on top of an ablator/drive layer on top of a surface of the hemispherical cavities; and
removing any excess from the deposition of shell layer and ablator/drive layer by a planarization polish.