# US 11,443,829 B2 · Memory system having non-volatile memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,443,829 B2 - Document ID: US11443829B2 - Status: Granted - Kind: B2 - Application number: 17/010,041 - Filed: 2020-09-02 - Published: 2021-09-23 - Granted: 2022-09-13 - Earliest claimed: 2020-03-19 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Ryo Yamaki; Yuki Komatsu - Web page: https://patentgrep.com/patent/US11443829B2 ## CPC - G11C 29/44: Indication or identification of errors, e.g. for repair - G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)} - G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit} - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G11C 11/5671: {using charge trapping in an insulator} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 29/021: {in voltage or current generators} - G11C 29/028: {with adaption or trimming of parameters} - G11C 29/50004: {of threshold voltage} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 2029/0411: {Online error correction} - G11C 2029/1202: {Word line control} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory system includes a non-volatile memory and a controller configured to divides an n-dimensional space into a plurality of regions by a plurality of hyperplanes, assign a representative point of a read level for reading data from a plurality of memory cells to each region, trace a branch node in the binary tree by determining whether a first read level is higher or lower than a voltage level at the branch node of the binary tree, determine a read level of a representative point assigned to a region correlated with a leaf node among the plurality of divided regions as a second read level corresponding to the first read level when reaching the leaf node of the binary tree by tracing the branch node in the binary tree, and cause the memory to read data of the cells by applying a voltage of the second read level. ## Claims ### Claim 1 A memory system comprising: a non-volatile memory including a word line and a plurality of memory cells connected to the word line; and a controller configured to: divide an n-dimensional space into a plurality of regions by a plurality of hyperplanes, where n is an integer of 2 or more; assign a representative point of a read level for reading data from a plurality of memory cells to each region; provide a binary tree for selecting any of the plurality of regions; trace a branch node in the binary tree by determining whether a first read level is higher or lower than a voltage level at the branch node of the binary tree; when determining the first read level is higher or lower than the voltage level of the branch node in the binary tree, determine whether a voltage difference between the first read level and the voltage level of the branch node is within a voltage margin or not; when reaching the leaf node of the binary tree by tracing the branch node in the binary tree, determine a read level of a representative point assigned to a region correlated with a leaf node among the plurality of divided regions as a second read level corresponding to the first read level, and cause the non-volatile memory to read data of the plurality of memory cells by applying a voltage of the determined second read level to the word line. ### Claim 2 (depends on 1) The memory system according to claim 1, wherein the controller is configured to adjust a voltage width of the voltage margin according to a bit error rate when reading data from the non-volatile memory. ### Claim 3 (depends on 1) The memory system according to claim 1, wherein the controller is configured to: when the first read level exceeds the range of the voltage margin to be higher or lower than the voltage level of the branch node, repeat processing for comparing the first read level with the voltage level of the branch node in descending order from the branch node on an upper side according to the binary tree, and when reaching the leaf node of the binary tree, determine the read level of the representative point assigned to the region correlated with the leaf node as the second read level. ### Claim 4 (depends on 1) The memory system according to claim 1, wherein the controller is configured to: when it is determined that a voltage difference between the first read level and the voltage level of the branch node is within the voltage margin, perform comparison with the first read level for all branch nodes on a lower side of the binary tree from the branch node determined to be within the voltage margin. ### Claim 5 (depends on 4) The memory system according to claim 4, further comprising: a node storage configured to store the branch node each time a branch node of a new search target is searched according to the binary tree, wherein the controller is configured to perform a voltage comparison with the first read level in order from the branch node stored most recently among the branch nodes stored in the node storage. ### Claim 6 (depends on 5) The memory system according to claim 5, wherein the controller is configured to perform the voltage comparison with the first read level in order from the branch node stored most recently until there are no branch nodes stored in the node storage. ### Claim 7 (depends on 5) The memory system according to claim 5, wherein the controller is configured to: when performing the voltage comparison of a voltage level of the branch node stored in the node storage with the first read level, determine whether the first read level is (i) higher or lower than the voltage level at the branch node, or (ii) within a range of the voltage margin corresponding to the voltage level of the branch node. ### Claim 8 (depends on 4) The memory system according to claim 4, wherein the controller is configured to: when the leaf node in the binary tree is searched, calculate a distance between the representative point in a region corresponding to the leaf node and the first read level and determine a read level of a representative point of a leaf node having a smallest distance as the second read level. ### Claim 9 (depends on 8) The memory system according to claim 8, wherein the controller is configured to: when calculating a distance between the first read level and the representative point, calculate a Euclidean distance, a Manhattan distance or a Chebyshev distance. ### Claim 10 (depends on 4) The memory system according to claim 4, wherein the controller is configured to stop searching from the branch node to a branch node on a lower side of the binary tree for a branch node having the voltage difference when the first read level is higher than or equal to a predetermined value. ### Claim 11 (depends on 1) The memory system according to claim 1, wherein the n-dimensional space is divided by a hyperplane perpendicular to an axis of each dimension. ### Claim 12 (depends on 1) The memory system according to claim 1, wherein the n-dimensional space is divided by a hyperplane in a direction inclined from an axis of each dimension. ### Claim 13 (depends on 12) The memory system according to claim 12, wherein the hyperplane is represented by a linear equation of the voltage level. ### Claim 14 (depends on 1) The memory system according to claim 1, wherein the first read level is a read voltage determined by shift read or Vth tracking performed by the controller. ### Claim 15 A method of operating a memory system comprising a non-volatile memory including a word line and a plurality of memory cells connected to the word line, the method comprising: dividing an n-dimensional space into a plurality of regions by a plurality of hyperplanes, where n is an integer of 2 or more; assigning a representative point of a read level for reading data from a plurality of memory cells to each region; providing a binary tree for selecting any of the plurality of regions; tracing a branch node in the binary tree by determining whether a first read level is higher or lower than a voltage level at the branch node of the binary tree; when determining the first read level is higher or lower than the voltage level of the branch node in the binary tree, determining whether a voltage difference between the first read level and the voltage level of the branch node is within a voltage margin or not; when reaching the leaf node of the binary tree by tracing the branch node in the binary tree, determining a read level of a representative point assigned to a region correlated with a leaf node among the plurality of divided regions as a second read level corresponding to the first read level, and causing the non-volatile memory to read data of the plurality of memory cells by applying a voltage of the determined second read level to the word line. ### Claim 16 (depends on 15) The method according to claim 15, further comprising: adjusting a voltage width of the voltage margin according to a bit error rate when reading data from the non-volatile memory. ### Claim 17 (depends on 15) The method according to claim 15, further comprising: when the first read level exceeds the range of the voltage margin to be higher or lower than the voltage level of the branch node, repeating processing for comparing the first read level with the voltage level of the branch node in descending order from the branch node on an upper side according to the binary tree, and when reaching the leaf node of the binary tree, determining the read level of the representative point assigned to the region correlated with the leaf node as the second read level. ### Claim 18 (depends on 15) The method according to claim 15, further comprising: when it is determined that a voltage difference between the first read level and the voltage level of the branch node is within the voltage margin, performing comparison with the first read level for all branch nodes on a lower side of the binary tree from the branch node determined to be within the voltage margin. ### Claim 19 (depends on 18) The method according to claim 18, further comprising: storing the branch node each time a branch node of a new search target is searched according to the binary tree, and performing a voltage comparison with the first read level in order from the branch node stored most recently among the branch nodes stored. ### Claim 20 (depends on 19) The method according to claim 19, further comprising: performing the voltage comparison with the first read level in order from the branch node stored most recently until there are no branch nodes stored.