# US 11,443,823 B2 · Method and circuit for scan dump of latch array

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- Number: US 11,443,823 B2
- Document ID: US11443823B2
- Status: Granted
- Kind: B2
- Application number: 17/468,066
- Filed: 2021-09-07
- Published: 2022-05-05
- Granted: 2022-09-13
- Earliest claimed: 2020-10-29
- Assignees: SambaNova Systems, Inc.
- Applicants: SambaNova Systems, Inc.
- Inventors: Thomas A. Ziaja; Uma Durairajan; Dinesh R. Amirtharaj
- Web page: https://patentgrep.com/patent/US11443823B2

## CPC

- G11C 29/32: Serial access; Scan testing
- G11C 5/066: {Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals}
- G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 11/419: Read-write [R-W] circuits
- G11C 29/1201: {comprising I/O circuitry}
- G11C 29/12015: {comprising clock generation or timing circuitry}
- G11C 29/36: Data generation devices, e.g. data inverters
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/56004: {Pattern generation}
- G01R 31/3172: {Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing}
- G01R 31/31723: {Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/3185: Reconfiguring for testing, e.g. LSSD, partitioning
- G01R 31/318536: {Scan chain arrangements, e.g. connections, test bus, analog signals}
- G01R 31/318541: {Scan latches or cell details}
- G01R 31/318544: {Scanning methods, algorithms and patterns (G01R31/3183 takes precedence)}
- G01R 31/318547: {Data generators or compressors}
- G01R 31/318566: {Comparators; Diagnosing the device under test}
- G01R 31/3187: Built-in tests
- G06F 11/27: Built-in tests
- G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 11/4082: {Address Buffers; level conversion circuits}
- G11C 29/48: Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
- G11C 2029/3202: {Scan chain}
- G11C 2207/007: Register arrays
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Testability of memory on integrated circuits is improved by connecting storage elements like latches in memory to scan chains and configuring memory for scan dump. The use of latches and similar compact storage elements to form scannable memory can extend the testability of high-density memory circuits on complex integrated circuits operable at high clock speeds. A scannable memory architecture includes an input buffer with active low buffer latches, and an array of active high storage latches, operated in coordination to enable incorporation of the memory into scan chains for ATPG/TT and scan dump testing modes.

## Claims

### Claim 1

A scannable memory circuit on an integrated circuit having a scan chain, comprising:
a row counter that increments once every N clock periods, dependent upon a scan enable signal, and resets after reaching a value of M, where both M and N are positive integers greater than 1;
an input buffer including N buffer latches enabled to load data during a first part of a clock of the clock periods;
an input selector having N outputs respectively coupled to N inputs of the N buffer latches of the input buffer, the input selector having N first inputs coupled to a first functional data path and N second inputs coupled to a feedback data path, the input selector configured to select between the N first inputs and the N second inputs based on the scan enable signal;
a clocking circuit, coupled to an output of the row counter and having a functional write address input and M row clock outputs, the clocking circuit configured to drive a selected row clock output of the M row clock outputs to an active state during a second part of the clock period, a selection of the selected row clock output based on the output of the row counter dependent upon the scan enable signal, or the functional write address input dependent on a write enable signal;
an array of M rows and N columns of storage elements, inputs of each storage element of a column of the N columns of storage elements coupled to an output of a corresponding buffer latch of the N buffer latches of the input buffer, each storage element of a row of the M rows of storage elements coupled to a respective row clock output of the M row clock outputs and enabled to load during an active state of the respective row clock output;
an output selector, coupled to the output of the row counter and having a functional read address input, M sets of N inputs respectively coupled to outputs of storage elements of the array of M rows and N columns of storage elements, and N outputs coupled to a second functional data path, the output selector configured to select between the M sets of N inputs based on the functional read address input or the output of the row counter dependent upon the scan enable signal;
a scan input for the scan chain coupled to a first line of the feedback data path, other lines of the feedback data path respectively coupled to different outputs of the N outputs of the output selector, wherein a particular output of the N outputs of the output selector is not coupled to the feedback data path; and
a scan output of the scan chain coupled to the particular output of the N outputs of the output selector.

### Claim 2 (depends on 1)

The scannable memory circuit of claim 1, further comprising:
a memory built-in self-testing (MBIST) circuit having a MBIST address output and a MBIST data output;
the input selector having third inputs coupled to the MBIST data output and configured to select the third inputs based on a MBIST enable signal; and
the clocking circuit coupled to the MBIST address output and configured to select the selected row clock output based on the MBIST address output dependent upon the MBIST enable signal.

### Claim 3 (depends on 1)

The scannable memory circuit of claim 1, wherein the clocking circuit is configured to select a particular row clock output as the selected row clock output based on a test mode enable signal.

### Claim 4 (depends on 1)

The scannable memory circuit of claim 1, further comprising:
control circuitry having outputs coupled to the functional write address input and the functional read address input, the control circuitry configured to arrange the array of M rows and N columns of storage elements as a First-In-First-Out (FIFO) buffer, a Look-Up-Table (LUT), or a Least Recently Used (LRU) buffer.

### Claim 5 (depends on 1)

The scannable memory circuit of claim 1, wherein the first part of the clock period is between a falling edge and a rising edge of an input clock signal, and the second part of the clock period is between a rising edge and a falling edge of the input clock signal.

### Claim 6 (depends on 1)

The scannable memory circuit of claim 1, wherein a buffer latch of the N buffer latches comprises a first transparent latch and a storage element in the array of storage elements coupled to the selected row clock output comprises a second transparent latch, and the first transparent latch and the second transparent latch are configured to act as a master-slave flip-flop in the scan chain.

### Claim 7 (depends on 1)

The scannable memory circuit of claim 1, wherein the storage elements in the array of storage elements respectively comprise static random-access memory (SRAM) bit cells.

### Claim 8 (depends on 1)

The scannable memory circuit of claim 1, wherein the storage elements in the array of storage elements respectively comprise a single transparent latch.

### Claim 9 (depends on 1)

The scannable memory circuit of claim 1, wherein the feedback data path is DIN(N−1:0) and the N outputs of the output bus are DOUT(N−1:0), wherein:
the scan input is coupled to DIN(N−1);
DOUT(N−1:1) are respectively coupled to DIN(N−2:0); and
DOUT(0) is coupled to the scan output.

### Claim 10 (depends on 1)

The scannable memory circuit of claim 1, wherein:
the clocking circuit is also coupled to an address output of a test pattern generator and responsive to a mode control input to determine the selected row clock output based on the functional write address input, the output of the row counter, the address output of the test pattern generator or a fixed scan mode row address.

### Claim 11

A method for scanning an array of storage elements using a scan chain, the array of storage elements arranged into M rows and N columns of storage elements, where both M and N are positive integers greater than 1, the method comprising:
providing a row scan address indicating a current active row of the array of storage elements;
(a) selecting outputs of storage elements of the current active row as an output having N lines, including sending an output bit of scan data from a particular line of the N lines of the output through a scan output of the scan chain;
(b) latching feedback data from a feedback data path having N lines into an input buffer in parallel during a first part of a clock period to ingest an input bit of scan data from a scan input for the scan chain, wherein a first line of the feedback data path is coupled to the scan input and other lines of the feedback data path are respectively coupled to different lines of the N lines of the output, wherein the particular line of the N lines of the output is not coupled to the feedback data path;
(c) latching the feedback data from the input buffer into the storage elements of the current active row in parallel during a second part of the clock period;
(d) repeating (b) and (c) for N−1 additional clock periods;
(e) updating the row scan address to change the current active row of the array of storage elements and resetting the row scan address in response to the updated row scan address equaling reaching a terminal value; and
(f) repeating (a) through (e) at least M times.

### Claim 12 (depends on 11)

The method of claim 11, wherein:
updating the row scan address comprises incrementing the row scan address by one;
resetting the row scan address comprises setting the row scan address to zero; and
the terminal value for the row scan address equals M.

### Claim 13 (depends on 11)

The method of claim 11, wherein:
the N lines of the feedback data path are DIN(N−1:0);
the N lines of the output are DOUT(N−1:0);
the scan input is coupled to DIN(N−1);
the scan output is coupled to DOUT(0); and
DIN(N−2:0) are respectively coupled to DOUT(N−1:1).

### Claim 14 (depends on 11)

The method of claim 11, wherein a bit of scan data flows from the scan input, through each storage element of the array of storage elements, to the scan output, in M×N clock periods.

### Claim 15 (depends on 11)

The method of claim 11, wherein at least some of (a) through (f) are performed in response to a scan enable signal being active.

### Claim 16 (depends on 15)

The method of claim 15, wherein the current active row is updated only if a scan dump enable signal is active and the current active row is set to a fixed row in response to the scan enable signal being active while the scan dump enable signal is inactive.

### Claim 17 (depends on 15)

The method of claim 15, further comprising:
receiving a functional read request with a read row address indicating a read row of the array of storage elements while the scan enable signal is inactive; and
selecting outputs of storage elements of the read row as the output and providing read data from the output to a functional data path.

### Claim 18 (depends on 15)

The method of claim 15, further comprising:
receiving a functional write request with a write row address indicating a write row of the array of storage elements while the scan enable signal is inactive;
latching write data from a functional data path into the input buffer in parallel during the first part of the clock period; and
latching the write data from the input buffer into the storage elements of the write row in parallel during a second part of the clock period.

### Claim 19 (depends on 15)

The method of claim 15, further comprising:
detecting a mode of operation for the array of storage elements having at least 4 modes of operation including a functional operation mode, a scan mode, a scan dump mode, and a self-test mode, wherein the scan enable signal is active during the scan mode and the scan dump mode;
in response to detecting that the mode of operation is the scan dump mode, performing (a) through (f);
in response to detecting that the mode of operation is the scan mode, setting the current active row to a fixed value and performing at least (a) through (d);
in response to detecting that the mode of operation is the self-test mode, latching test data from a memory built-in self-testing (MBIST) circuit into the input buffer in parallel during the first part of the clock period, using an address from the MBIST circuit to determine a test row of the array of storage elements, and latching the test data from the input buffer into the storage elements of the test row in parallel during a second part of the clock period; and
in response to detecting that the mode of operation is the functional operation mode;
in response to a functional read request, selecting outputs of storage elements of a read row selected based on a functional read address as the output and providing read data from the output to a functional data path; and
in response to a functional write request, latching write data from a functional data path into the input buffer in parallel during the first part of the clock period, and latching the write data from the input buffer into the storage elements of a write row in parallel during a second part of the clock period, wherein the write row is selected based on a functional write address.

### Claim 20 (depends on 11)

The method of claim 11, wherein the first part of the clock period is between a falling edge and a rising edge of an input clock signal, and the second part of the clock period is between a rising edge and a falling edge of the input clock signal.