# US 11,443,820 B2 · Memory device, memory address decoder, system, and related method for memory attack detection

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- Number: US 11,443,820 B2
- Document ID: US11443820B2
- Status: Granted
- Kind: B2
- Application number: 15/956,526
- Filed: 2018-04-18
- Published: 2019-07-25
- Granted: 2022-09-13
- Earliest claimed: 2018-01-23
- Assignees: Microchip Technology Incorporated
- Applicants: Microchip Technology Incorporated
- Inventors: Lorenzo Bedarida; Simone Bartoli; Albert S. Weiner
- Web page: https://patentgrep.com/patent/US11443820B2

## CPC

- G11C 29/024: {in decoders}
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
- G11C 8/10: Decoders
- G11C 8/20: Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 29/38: Response verification devices
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory device, memory address decoder, a memory system and related method for memory attack detection are disclosed. An apparatus includes a memory decoder include multiple stages in a decoding path configured to generate a select signal from an input address signal, and fault detecting logic operably coupled with the memory decoder and configured to receive feedback signals distributed from the multiple stages indicative of a fault along the decoding path.

## Claims

### Claim 1

An apparatus, comprising:
a memory address decoder including multiple stages in a decoding path to generate a select signal from an input address signal, wherein each of at least two stages of the multiple stages includes respective integrated fault detection circuitry to:
detect an erred bit along a respective decoding path of the at least two stages; and
generate a feedback signal indicative of the detected erred bit, and
fault detecting logic operably coupled with the memory address decoder to receive the respective feedback signals distributed from the multiple stages indicative of a fault along the decoding path, the received feedback signals including feedback signals generated by the respective integrated fault detection circuitry of the at least two stages of the multiple stages.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the memory address decoder includes at least one global decoder, at least one local decoder, and at least one row decoder.

### Claim 3 (depends on 2)

The apparatus of claim 2, comprising a global encoder to receive an output from the at least one global decoder and generate a replica input address signal.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the fault detecting logic is to compare the replica input address signal and the input address signal to determine the fault is present.

### Claim 5 (depends on 3)

The apparatus of claim 3, wherein the at least one local decoder is to perform an internal comparison of each bit of its decoder output path with another bit within respective integrated fault detection circuitry coupled to the at least one local decoder.

### Claim 6 (depends on 3)

The apparatus of claim 3, wherein the at least one row decoder is to perform an internal comparison of each bit of its decoder output path with another bit within respective integrated fault detection circuitry coupled to the at least one row decoder.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the apparatus is a memory device.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the memory address decoder includes a row decoder.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the memory address decoder includes a column decoder.

### Claim 10 (depends on 1)

The apparatus of claim 1, comprising a microcontroller coupled with a memory device.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the microcontroller includes the fault detecting logic and the memory device includes the memory address decoder.

### Claim 12 (depends on 10)

The apparatus of claim 10, wherein the memory device includes both the fault detecting logic and the memory address decoder.

### Claim 13

A method, the method comprising:
decoding an input signal via a memory address decoder including multiple stages in a decoding path to generate a select signal from an input address signal;
performing fault detecting within at least two stages of the multiple stages in the decoding path;
detecting erred bits along a respective decoding path of the at least two stages at least partially responsive to the fault detecting;
generating feedback signals indicative of the detected erred bits, the feedback signals distributed within the multiple stages; and
receiving, at fault detecting logic, feedback signals indicative of a fault along the decoding path, the received feedback signals comprising the generated feedback signals distributed within the multiple stages.

### Claim 14 (depends on 13)

The method of claim 13, wherein receiving, at fault detecting logic the feedback signals comprises receiving the feedback signals at fault detecting logic located within a memory device.

### Claim 15 (depends on 13)

The method of claim 13, wherein receiving, at fault detecting logic, the feedback signals comprises receiving the feedback signals at fault detecting logic located within a microcontroller operably coupled with a memory device.

### Claim 16 (depends on 13)

The method of claim 13, wherein receiving, at fault detecting logic, the feedback signals comprises receiving the feedback signals at fault detecting logic located within a device external to the memory device.

### Claim 17 (depends on 13)

The method of claim 13, comprising generating the feedback signals within at least one of a row decoder or a column decoder operably coupled to a memory array of a memory device.

### Claim 18 (depends on 1)

The apparatus of claim 1, wherein the fault detecting logic is to associate the fault with a given stage of the multiple stages responsive to the feedback signal received from the given stage.