# US 11,443,818 B2 · Safety and correctness data reading and programming in a non-volatile memory device

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- Number: US 11,443,818 B2
- Document ID: US11443818B2
- Status: Granted
- Kind: B2
- Application number: 16/624,728
- Filed: 2019-05-31
- Published: 2021-12-30
- Granted: 2022-09-13
- Earliest claimed: 2019-05-31
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Antonino Mondello; Alberto Troia
- Web page: https://patentgrep.com/patent/US11443818B2

## CPC

- G11C 16/3495: {Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically}
- G11C 16/102: {External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators}
- G11C 16/16: for erasing blocks, e.g. arrays, words, groups
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/3472: {Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure}
- G11C 29/021: {in voltage or current generators}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/24: Accessing extra cells, e.g. dummy cells or redundant cells
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 7/04: with means for avoiding disturbances due to temperature effects
- G11C 16/30: Power supply circuits
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present disclosure relates to a method for improving the safety of the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprising: storing in a dummy row of said memory block at least a known pattern; performing some reading cycles changing the read trimming parameters up to the moment wherein said known value is read correctly; adopting the trimming parameters of the correct reading for the subsequent reading phases. The disclosure further relates to a memory device structured for implementing the above method.

## Claims

### Claim 1

A non-volatile memory device comprising:
an array of memory cells with a plurality of memory blocks;
a dummy row corresponding to each block of the plurality of memory blocks for storing a corresponding known pattern and a read trimming parameter for reading the known pattern outside of an addressable space of the corresponding memory block of the plurality of memory blocks;
a controller of the memory device configured to trigger a detection of a thermal drift in a memory block of the plurality of memory blocks utilizing a known pattern stored in a dummy row corresponding to the memory block responsive to a detection of a temperature variation of the memory device;
sensing circuitry, driven by the controller, for reading the known pattern stored in the dummy row corresponding to the memory block by performing reading cycles and changing the read trimming parameter stored in the dummy row for reading the known pattern up to a moment a value of the known pattern stored in the dummy row corresponding to the memory block is read correctly;
determining in a subsequent reading phase, based on an absence of the read trimming parameter in the dummy row utilizable to read the known pattern in the dummy row, a power loss has occurred; and
erasing the whole memory block responsive to the determination the power loss has occurred.

### Claim 2 (depends on 1)

The non-volatile memory device of claim 1, wherein the known pattern stored in the dummy row corresponding to the memory block is known to the controller of the memory device, and wherein the known pattern stored in the dummy row corresponding to the memory block includes an equal number of bits programmed (‘0’) and erased (‘1’).

### Claim 3 (depends on 1)

The non-volatile memory device of claim 1, wherein the changed trimming parameter corresponds to a set temperature value recorded in a programmable register.

### Claim 4 (depends on 1)

The non-volatile memory device of claim 1, wherein the dummy row corresponding to the memory block is configured to store internal block variables of a reading phase, a programming phase, or an erasing phase.

### Claim 5 (depends on 4)

The non-volatile memory device of claim 4, wherein the internal block variables include reading pulses and target voltages applied to the memory block during the reading phase.

### Claim 6 (depends on 1)

The non-volatile memory device of claim 1, utilizing the trimming parameter utilized when the known pattern stored in the dummy row corresponding to the memory block is read correctly to select a value of a read reference cell.

### Claim 7 (depends on 1)

The non-volatile memory device of claim 1, wherein the dummy row corresponding to the memory block is provided in another memory block of the array of memory cells.

### Claim 8

An apparatus, comprising:
a host device, comprising a system-on-chip (SoC), wherein the SoC is configured to perform error correction operations on data retrieved from an addressable space of a non-volatile memory component;
the non-volatile memory component, comprising a structure independent from the SoC but coupled to the host device, including an array of memory cells with a plurality of memory blocks, wherein a memory block of the plurality of memory blocks stores data in its addressable space;
a dummy row, corresponding to the memory block of the plurality of memory blocks, storing a known pattern and trimming parameters to read the known pattern outside the addressable space of the memory block;
a controller of the memory component configured to trigger a detection of thermal drift or aging utilizing the known pattern stored in the dummy row responsive to a number of ECC bits from correction of the data retrieved from the addressable space of the non-volatile memory component by the SoC exceeding a threshold;
sensing circuitry, driven by the controller, for reading the known pattern stored in the dummy row by performing a reading cycle and changing a read trimming parameter up to the moment when the value of the known pattern is read correctly utilizing the read trimming pattern;
determining in a subsequent reading phase, based on an absence of the read trimming parameter in the dummy row utilizable to read the known pattern in the dummy row, a power loss has occurred; and
erasing the whole memory block responsive to the determination the power loss has occurred.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the dummy row is configured to store internal block variables of a reading phase and an erasing phase.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the internal block variables include reading pulses or target voltages applied to the memory block during the reading phase.

### Claim 11 (depends on 8)

The apparatus of claim 8, wherein the array of memory cells includes a plurality of independently addressable memory blocks, wherein each of the plurality of independently addressable memory blocks block includes at least 256 rows of memory cells and each row includes at least sixteen super pages each formed by a combination of data bits, address bits and ECC bits of a memory location.

### Claim 12 (depends on 8)

The apparatus of claim 8, wherein the non-volatile memory component partially overlaps the SoC, wherein the non-volatile memory component comprises a plurality of pads arranged over a memory array in a configuration that, when the non-volatile memory component is reversed, the plurality of pads are faced to corresponding pads of the SoC.

### Claim 13

A method, comprising:
storing a known pattern in a dummy row corresponding to a memory block of a plurality of memory blocks of an array of memory cells, wherein the memory block stores data in an addressable location of the memory block and wherein the dummy row stores the known pattern outside an addressable space of the memory block;
performing reading cycles and changing a trimming parameter stored in the dummy row up to a moment when the known pattern is read correctly utilizing the trimming parameter;
adopting the changed trimming parameter of the correct reading of the known pattern for subsequent reading phases of the addressable location;
determining in a subsequent reading phase, based on an absence of the trimming parameter in the dummy row utilizable to read the known pattern, a power loss has occurred; and
erasing the whole memory block responsive to the determination the power loss has occurred.

### Claim 14 (depends on 13)

The method of claim 13, wherein the changed trimming parameter of the correct reading corresponds to a set temperature value recorded in a programmable register.

### Claim 15 (depends on 13)

The method of claim 13, wherein adopting the trimming parameter is performed responsive to the known value being read correctly.

### Claim 16 (depends on 13)

The method of claim 13, wherein the known pattern includes values in hexadecimal form comprising the same amount of “0” logic values and “1” logic values.

### Claim 17 (depends on 13)

The method of claim 13, wherein the reading cycles are performed automatically when an increased number of ECC bits is representative of an excessive number of wrong reading from a non-volatile memory device including the array of memory cells.

### Claim 18 (depends on 13)

The method of claim 13, wherein the reading cycles are performed periodically.

### Claim 19 (depends on 13)

The method of claim 13, wherein the dummy row is configured to store information indicative of a fail of an erase operation.

### Claim 20 (depends on 13)

The method of claim 13, further comprising starting an erasing phase on the memory block based on retrieving internal block variables of a previous erasing phase from the dummy row.